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[194.187.74.233]) by smtp.gmail.com with ESMTPSA id m13-v6sm1160960lfj.39.2018.09.26.12.31.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Sep 2018 12:31:14 -0700 (PDT) From: =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= To: Linus Walleij , linux-gpio@vger.kernel.org, Rob Herring , devicetree@vger.kernel.org Subject: [PATCH V3 1/2] dt-bindings: pinctrl: document Broadcom Northstar pin mux controller Date: Wed, 26 Sep 2018 21:31:02 +0200 Message-Id: <20180926193103.21241-1-zajec5@gmail.com> X-Mailer: git-send-email 2.13.7 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180926_123149_404646_7E63B019 X-CRM114-Status: GOOD ( 14.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Florian Fainelli , Scott Branden , Ray Jui , bcm-kernel-feedback-list@broadcom.com, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rafał Miłecki Northstar has mux controller just like Northstar Plus and Northstar2. It's a bit different though (different registers & pins) so it requires its own binding. It's needed to allow other block bindings specify required mux setup. Signed-off-by: Rafał Miłecki Reviewed-by: Florian Fainelli --- V2: Use "cru_gpio_control" Add more functions & groups Include Florian's Reviewed-by V3: Use 3 different bindings as available pins depend on the chipset. Strings match Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.txt --- .../bindings/pinctrl/brcm,bcm4708-pinmux.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt new file mode 100644 index 000000000000..af906f196e8c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt @@ -0,0 +1,42 @@ +Broadcom Northstar pins mux controller + +Some of Northstar SoCs's pins can be used for various purposes thanks to the mux +controller. This binding allows describing mux controller and listing available +functions. They can be referenced later by other bindings to let system +configure controller correctly. + +A list of pins varies across chipsets so few bindings are available. + +Required properties: +- compatible: must be one of: + "brcm,bcm4708-pinmux" + "brcm,bcm4709-pinmux" + "brcm,bcm53012-pinmux" +- reg: iomem address range of CRU (Central Resource Unit) pin registers +- reg-names: "cru_gpio_control" - the only needed & supported reg right now + +Functions and their groups available for all chipsets: +- "spi": "spi_grp" +- "i2c": "i2c_grp" +- "pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp" +- "uart1": "uart1_grp" + +Additionally available on BCM4709 and BCM53012: +- "mdio": "mdio_grp" +- "uart2": "uart2_grp" +- "sdio": "sdio_pwr_grp", "sdio_1p8v_grp" + +For documentation of subnodes see: +Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +Example: + pinctrl@1800c1c0 { + compatible = "brcm,bcm4708-pinmux"; + reg = <0x1800c1c0 0x24>; + reg-names = "cru_gpio_control"; + + spi { + function = "spi"; + groups = "spi_grp"; + }; + };