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b=QfI1AMAHbCVTvtByU9IFSAGAfyUuN6ly2NxKdumiOZ317lu74aqNrmYqsBytUfkXKa 2UmaA+VyaIoUiaIlnPfPAPZSeGqIttqYQ0T23TrwUUseMxJ4fW/lpgLyfwJz85OPoa6h sA9M/A+vkTTvsf3M8BtaohhAWG9ZNvwQ4UB+rfr6E5jo9oA0bP3xgr7fEe/YaG0eNQmQ rRZlbAFCuWSxTEkbaK64aj/JeNG2xWWSAhyqvPsBepsNnu051feIBt1uJy3zxbizDXyo TIBZFrWhJ+PJtEJYYSQGNPF9eDI3iBNhS8R/qYXFKgHYbTqj5unAuCb14ycmphIKTO2M QQjA== X-Gm-Message-State: ABuFfojkRpyB/go+i4QGZIJAIGoXc1rlpOKl+hD5+CzzUbydMCN0m5DR puTs9f2+BdJf2fVk4ju35jqGvA== X-Google-Smtp-Source: ACcGV61n0c+VbTj7yWqStK2eKWDmJ1dD6rYcg2o4jH6PZOroiMKqXdoK8Hi7z6fVU+zvRIfy+65I7w== X-Received: by 2002:a17:902:7109:: with SMTP id a9-v6mr26985609pll.310.1539064093897; Mon, 08 Oct 2018 22:48:13 -0700 (PDT) Received: from joelaf.mtv.corp.google.com ([2620:0:1000:1601:3aef:314f:b9ea:889f]) by smtp.gmail.com with ESMTPSA id a15-v6sm16886234pff.8.2018.10.08.22.48.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 Oct 2018 22:48:12 -0700 (PDT) From: "Joel Fernandes (Google)" To: stable@vger.kernel.org Subject: [PATCH 5/7] dmaengine: stm32-dma: fix DMA IRQ status handling Date: Mon, 8 Oct 2018 22:47:50 -0700 Message-Id: <20181009054752.145978-6-joel@joelfernandes.org> X-Mailer: git-send-email 2.19.0.605.g01d371f741-goog In-Reply-To: <20181009054752.145978-1-joel@joelfernandes.org> References: <20181009054752.145978-1-joel@joelfernandes.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181008_224824_774167_5A2FD97F X-CRM114-Status: GOOD ( 12.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexandre Torgue , Vinod Koul , gregkh@linuxfoundation.org, linux-kernel@vger.kernel.org, Pierre Yves MORDRET , "Joel Fernandes \(Google\)" , Maxime Coquelin , dmaengine@vger.kernel.org, Dan Williams , "moderated list:ARM/STM32 ARCHITECTURE" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Pierre Yves MORDRET Update the way Transfer Complete and Half Transfer Complete status are acknowledge. Even if HTI is not enabled its status is shown when reading registers, driver has to clear it gently and not raise an error. Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Vinod Koul --- drivers/dma/stm32-dma.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/dma/stm32-dma.c b/drivers/dma/stm32-dma.c index 21ad359a5a59..b40486454a2c 100644 --- a/drivers/dma/stm32-dma.c +++ b/drivers/dma/stm32-dma.c @@ -34,9 +34,14 @@ #define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */ #define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */ #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */ +#define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */ #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */ #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */ +#define STM32_DMA_MASKI (STM32_DMA_TCI \ + | STM32_DMA_TEI \ + | STM32_DMA_DMEI \ + | STM32_DMA_FEI) /* DMA Stream x Configuration Register */ #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */ @@ -643,13 +648,29 @@ static irqreturn_t stm32_dma_chan_irq(int irq, void *devid) status = stm32_dma_irq_status(chan); scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); - if ((status & STM32_DMA_TCI) && (scr & STM32_DMA_SCR_TCIE)) { + if (status & STM32_DMA_TCI) { stm32_dma_irq_clear(chan, STM32_DMA_TCI); - stm32_dma_handle_chan_done(chan); - - } else { + if (scr & STM32_DMA_SCR_TCIE) + stm32_dma_handle_chan_done(chan); + status &= ~STM32_DMA_TCI; + } + if (status & STM32_DMA_HTI) { + stm32_dma_irq_clear(chan, STM32_DMA_HTI); + status &= ~STM32_DMA_HTI; + } + if (status & STM32_DMA_FEI) { + stm32_dma_irq_clear(chan, STM32_DMA_FEI); + status &= ~STM32_DMA_FEI; + if (!(scr & STM32_DMA_SCR_EN)) + dev_err(chan2dev(chan), "FIFO Error\n"); + else + dev_dbg(chan2dev(chan), "FIFO over/underrun\n"); + } + if (status) { stm32_dma_irq_clear(chan, status); dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status); + if (!(scr & STM32_DMA_SCR_EN)) + dev_err(chan2dev(chan), "chan disabled by HW\n"); } spin_unlock(&chan->vchan.lock);