From patchwork Wed Oct 17 05:59:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Ma X-Patchwork-Id: 10644587 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3E02C109C for ; Wed, 17 Oct 2018 06:07:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2D6D829D05 for ; Wed, 17 Oct 2018 06:07:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 20B282A668; Wed, 17 Oct 2018 06:07:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9C8402A578 for ; Wed, 17 Oct 2018 06:07:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=50sD6uOjrphdOCTHNsHTC4/Oi+P8LWcg2Jirdr+bRxQ=; b=RiIrd1Llw1QbhNMUQNUU0RwSo4 ysm8lG3NnMZjpUSTPSI9FTUmV22SwxrSjxejclycabbViqLiYkgbEme28KDYwEXdy7QoQLxZEV979 HMcb04jkKU0xJqFStVSRE1UWR6VJVFDKNRJO4O5j6qUHg1KRM+Eo0tCG96uYCLl54/CMKzIRU10hG 5smN+FeikrRStoQZsdCsQSFOzddk6IxssXS47kKc6jy+bQekTXr8QtOChSiUtZumHXCMZpFAt7oAa kNjHYGO2Rb4wOU6vZYAo7qdicMG2TDQZuJWGPzFz8moHehRfnpuU5IVG02s03eGEQr/rUmdGvXst/ L9GFxotQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gCez4-00083d-Ga; Wed, 17 Oct 2018 06:07:06 +0000 Received: from merlin.infradead.org ([2001:8b0:10b:1231::1]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gCewH-0005dH-4M for linux-arm-kernel@bombadil.infradead.org; Wed, 17 Oct 2018 06:04:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=merlin.20170209; h=References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=3i/NmIgJq+glKmCBbuC9eriXD4E/SWR2Zh37QqDYraA=; b=LxHE571TlUi/e+hqxIQMTFGdb LDAjfUYdFmDUgflwsN9JJ9s1hI46N+FmBlWQqliE2uLMJ+R9HovFRxMGdHwiWY67ybaw1thm58u1A OrhdHTDB/ONK+Uv3rC5yN39TxjkTGvpyaDQpTAblzlaIVitr8YFMFby1AmiawS85554x8yB/orr6V OdUzOdvFLhIN3/wtmiTj3nEvvFulg4fcv0RD/deCIDFZ/YJfvK7C10pI9wnmxVoyIhRuerbpxOny+ vkbrJpKDNLRYzhm3sZ9x0pjs2dpxRV17ToBHNr6no5fidSDrhEF1Af5/BCT/+YCjSoAbjh5rl+2W+ 1Ups2pasw==; Received: from inva020.nxp.com ([92.121.34.13]) by merlin.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gCewE-0006df-46 for linux-arm-kernel@lists.infradead.org; Wed, 17 Oct 2018 06:04:11 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 55E1C1A01C3; Wed, 17 Oct 2018 08:03:56 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id BE7481A01E2; Wed, 17 Oct 2018 08:03:49 +0200 (CEST) Received: from titan.ap.freescale.net (TITAN.ap.freescale.net [10.192.208.233]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id C453E402F0; Wed, 17 Oct 2018 14:03:41 +0800 (SGT) From: Peng Ma To: vkoul@kernel.org Subject: [v9 2/7] dmaengine: fsldma: Adding macro FSL_DMA_IN/OUT implement for ARM platform Date: Wed, 17 Oct 2018 13:59:52 +0800 Message-Id: <20181017055957.542-2-peng.ma@nxp.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20181017055957.542-1-peng.ma@nxp.com> References: <20181017055957.542-1-peng.ma@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181017_020410_358895_1F3B5776 X-CRM114-Status: UNSURE ( 9.32 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Wen He , linuxppc-dev@lists.ozlabs.org, Peng Ma , linux-kernel@vger.kernel.org, leoyang.li@nxp.com, zw@zh-kernel.org, robh+dt@kernel.org, dmaengine@vger.kernel.org, dan.j.williams@intel.com, shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add the macro FSL_DMA_IN/OUT implement for ARM platform. Signed-off-by: Wen He Signed-off-by: Peng Ma --- change in v9: - rewrite function fsl_ioread64 and fsl_ioread64be to make a better read drivers/dma/fsldma.h | 59 +++++++++++++++++++++++++++++++++---------------- 1 files changed, 40 insertions(+), 19 deletions(-) diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h index 982845b..f635bc1 100644 --- a/drivers/dma/fsldma.h +++ b/drivers/dma/fsldma.h @@ -196,39 +196,60 @@ struct fsldma_chan { #define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node) #define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx) +#ifdef CONFIG_PPC +#define fsl_ioread32(p) in_le32(p) +#define fsl_ioread32be(p) in_be32(p) +#define fsl_iowrite32(v, p) out_le32(p, v) +#define fsl_iowrite32be(v, p) out_be32(p, v) + #ifndef __powerpc64__ -static u64 in_be64(const u64 __iomem *addr) +static u64 fsl_ioread64(const u64 __iomem *addr) { - return ((u64)in_be32((u32 __iomem *)addr) << 32) | - (in_be32((u32 __iomem *)addr + 1)); + u32 fsl_addr = lower_32_bits(addr); + + return in_le32(fsl_addr) | in_le32(fsl_addr + 1) << 32; } -static void out_be64(u64 __iomem *addr, u64 val) +static void fsl_iowrite64(u64 val, u64 __iomem *addr) { - out_be32((u32 __iomem *)addr, val >> 32); - out_be32((u32 __iomem *)addr + 1, (u32)val); + out_le32((u32 __iomem *)addr + 1, val >> 32); + out_le32((u32 __iomem *)addr, (u32)val); } -/* There is no asm instructions for 64 bits reverse loads and stores */ -static u64 in_le64(const u64 __iomem *addr) +static u64 fsl_ioread64be(const u64 __iomem *addr) { - return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) | - (in_le32((u32 __iomem *)addr)); + u32 fsl_addr = lower_32_bits(addr); + + return in_be32(fsl_addr + 1) | in_be32(fsl_addr) << 32; } -static void out_le64(u64 __iomem *addr, u64 val) +static void fsl_iowrite64be(u64 val, u64 __iomem *addr) { - out_le32((u32 __iomem *)addr + 1, val >> 32); - out_le32((u32 __iomem *)addr, (u32)val); + out_be32((u32 __iomem *)addr, val >> 32); + out_be32((u32 __iomem *)addr + 1, (u32)val); } #endif +#endif -#define FSL_DMA_IN(fsl_chan, addr, width) \ - (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ - in_be##width(addr) : in_le##width(addr)) -#define FSL_DMA_OUT(fsl_chan, addr, val, width) \ - (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ - out_be##width(addr, val) : out_le##width(addr, val)) +#if defined(CONFIG_ARM64) || defined(CONFIG_ARM) +#define fsl_ioread32(p) ioread32(p) +#define fsl_ioread32be(p) ioread32be(p) +#define fsl_iowrite32(v, p) iowrite32(v, p) +#define fsl_iowrite32be(v, p) iowrite32be(v, p) +#define fsl_ioread64(p) ioread64(p) +#define fsl_ioread64be(p) ioread64be(p) +#define fsl_iowrite64(v, p) iowrite64(v, p) +#define fsl_iowrite64be(v, p) iowrite64be(v, p) +#endif + +#define FSL_DMA_IN(fsl_dma, addr, width) \ + (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ? \ + fsl_ioread##width##be(addr) : fsl_ioread##width(addr)) + +#define FSL_DMA_OUT(fsl_dma, addr, val, width) \ + (((fsl_dma)->feature & FSL_DMA_BIG_ENDIAN) ? \ + fsl_iowrite##width##be(val, addr) : fsl_iowrite \ + ##width(val, addr)) #define DMA_TO_CPU(fsl_chan, d, width) \ (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \