From patchwork Fri Oct 19 12:58:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 10649531 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 21D3313A4 for ; Fri, 19 Oct 2018 13:45:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1098328C28 for ; Fri, 19 Oct 2018 13:45:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0EADF28C1D; Fri, 19 Oct 2018 13:45:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 89F0028C13 for ; Fri, 19 Oct 2018 13:45:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=i6WQWAfCjEDyaP013puNnTkH2XmsS4AGwVFwaJk32m4=; b=G8iVGppcD+s9U/ Hrv1dhF8RnxzRl3CLOAW/jnCzQ+kuOm+oMxl0fGPYKpDOmUF9a9yotJeTc0A23DP4W+1X8aZLCDoH HtxpKj9/Z8T8OLwnZtVa6bn9XLZbyORpS0/rqUeukcvh2w4ouOItSODJAI8miuEjmSdgaxu9G0N+P GjHiut2lD4zMgNm9HUHmq18vrVMKurluY5EiEx3pIHNDUaCVqLHqPT7MXIqLfmBbOMt+J9+e7r3eE Wj6OijGSgvl7w60elsc+XUQHDvIGmmOVsXq9B163T9mxOXI9KZvHfdyWZFNOPXCoo5IEVKwg111/I KMcVpYlAtmrhN80bTLWw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gDV5Z-0003ye-Kn; Fri, 19 Oct 2018 13:45:17 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gDUc6-0000Eb-I2 for linux-arm-kernel@bombadil.infradead.org; Fri, 19 Oct 2018 13:14:50 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=uFqsBkOX2XileRgmHkd1sVIOsO2KsUfXTcAzU+yKcRY=; b=rVS1RcvykXQi51betX47o2o88G H6Qw++9rMUzkG4arLPklne8M8TRxMApoOcRFVE3uawcNq/u7gWNG4ENibblqoEEAtHy+YksCuLmpC 4eSJaHpZNVnLngs6UmU0eewFnpmLCzmhmG2Hllh6ZtXpDzmZYRgSDX7vANCXqPNSxKdcoGUNKVmmW Qj9rSwTOisQmFZLMmJgMcI6aFsnGyeNVDVG8NNWx35TE2gCeVWbBALeCEdkL0LpTkeMeTtRG+3e/M thBsun6+8Yms/s4kqkQKJEFj4K6Mf7POGIdHIvj3JcNJKVJnkVrRO+DVeZS9+34pbxmgzO32HXoTl Ji2JedLQ==; Received: from foss.arm.com ([217.140.101.70]) by casper.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gDUNJ-0000Hl-CA for linux-arm-kernel@lists.infradead.org; Fri, 19 Oct 2018 12:59:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2B7051650; Fri, 19 Oct 2018 05:59:30 -0700 (PDT) Received: from filthy-habits.cambridge.arm.com (filthy-habits.cambridge.arm.com [10.1.196.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 81DA43F71D; Fri, 19 Oct 2018 05:59:27 -0700 (PDT) From: Marc Zyngier To: Paolo Bonzini , =?utf-8?b?UmFkaW0gS3LEjW3DocWZ?= Subject: [PATCH 04/26] arm64: Add a helper for PARange to physical shift conversion Date: Fri, 19 Oct 2018 13:58:39 +0100 Message-Id: <20181019125901.185478-5-marc.zyngier@arm.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181019125901.185478-1-marc.zyngier@arm.com> References: <20181019125901.185478-1-marc.zyngier@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181019_135933_549472_B98375D3 X-CRM114-Status: GOOD ( 14.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , zhong jiang , kvm@vger.kernel.org, Suzuki K Poulose , Catalin Marinas , Punit Agrawal , Christoffer Dall , Kristina Martsenko , Dongjiu Geng , Eric Auger , James Morse , Robin Murphy , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Suzuki K Poulose On arm64, ID_AA64MMFR0_EL1.PARange encodes the maximum Physical Address range supported by the CPU. Add a helper to decode this to actual physical shift. If we hit an unallocated value, return the maximum range supported by the kernel. This will be used by KVM to set the VTCR_EL2.T0SZ, as it is about to move its place. Having this helper keeps the code movement cleaner. Cc: Marc Zyngier Cc: James Morse Cc: Christoffer Dall Acked-by: Catalin Marinas Reviewed-by: Eric Auger Signed-off-by: Suzuki K Poulose Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/cpufeature.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 1717ba1db35d..072cc1c970c2 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -530,6 +530,26 @@ void arm64_set_ssbd_mitigation(bool state); static inline void arm64_set_ssbd_mitigation(bool state) {} #endif +static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange) +{ + switch (parange) { + case 0: return 32; + case 1: return 36; + case 2: return 40; + case 3: return 42; + case 4: return 44; + case 5: return 48; + case 6: return 52; + /* + * A future PE could use a value unknown to the kernel. + * However, by the "D10.1.4 Principles of the ID scheme + * for fields in ID registers", ARM DDI 0487C.a, any new + * value is guaranteed to be higher than what we know already. + * As a safe limit, we return the limit supported by the kernel. + */ + default: return CONFIG_ARM64_PA_BITS; + } +} #endif /* __ASSEMBLY__ */ #endif