@@ -44,13 +44,4 @@ static inline int cpu_is_pxa910(void)
#define cpu_is_pxa910() (0)
#endif
-#ifdef CONFIG_CPU_MMP2
-static inline int cpu_is_mmp2(void)
-{
- return (((read_cpuid_id() >> 8) & 0xff) == 0x58);
-}
-#else
-#define cpu_is_mmp2() (0)
-#endif
-
#endif /* __ASM_MACH_CPUTYPE_H */
@@ -104,7 +104,7 @@ void __init mmp2_init_irq(void)
static int __init mmp2_init(void)
{
- if (cpu_is_mmp2()) {
+ if (cpu_is_pj4()) {
#ifdef CONFIG_CACHE_TAUROS2
tauros2_init(0);
#endif
@@ -220,7 +220,7 @@ static int __init mmp2_pm_init(void)
{
uint32_t apcr;
- if (!cpu_is_mmp2())
+ if (!cpu_is_pj4())
return -EIO;
suspend_set_ops(&mmp2_pm_ops);
@@ -163,7 +163,7 @@ static void __init timer_config(void)
__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
- ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
+ ccr &= (cpu_is_pj4()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
__raw_writel(ccr, mmp_timer_base + TMR_CCR);