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Tue, 13 Nov 2018 11:22:42 +0100 (CET) From: Lubomir Rintel To: Mark Brown , Geert Uytterhoeven Subject: [PATCH v3 6/6] spi: pxa2xx: Deal with the leftover garbage in TXFIFO Date: Tue, 13 Nov 2018 11:22:28 +0100 Message-Id: <20181113102228.820214-7-lkundrak@v3.sk> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181113102228.820214-1-lkundrak@v3.sk> References: <20181113102228.820214-1-lkundrak@v3.sk> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181113_052317_742465_6F26E6FB X-CRM114-Status: GOOD ( 13.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Eric Miao , James Cameron , linux-kernel@vger.kernel.org, Haojian Zhuang , linux-spi@vger.kernel.org, Lubomir Rintel , Rob Herring , linux-arm-kernel@lists.infradead.org, Robert Jarzmik , Daniel Mack Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP There doesn't seem to be a way to empty TXFIFO on MMP2. The datasheet is super-secret and the method described in Armada 16x manual won't work: "The TXFIFO and RXFIFO are cleared to 0b0 when the SSPx port is reset or disabled (by writing a 0b0 to the field in the SSP Control Register 0)." # devmem 0xd4037008 # read SSSR 0x0000F204 # devmem 0xd4037000 32 0x07 # SSE off in SSCR0 # devmem 0xd4037000 32 0x87 # SSE on # devmem 0xd4037008 0x0000F204 ^ TXFIFO level is still 2. Sigh. The OLPC 1.75 boot firmware leaves two bytes in the TXFIFO. Those are basically throwaway bytes used in response to the messages from the EC. The OLPC kernel copes with this by power-cycling the hardware. Perhaps the firmware should do this instead. Other than that, there's not much we can do other than complain loudly until the garbage gets drained and discard the actual data... For the OLPC EC this will work just fine and pushing more data to TXFIFO would break further transactions. Signed-off-by: Lubomir Rintel Acked-by: Pavel Machek --- Changes since v1: - Fixed a commit message typo (spotted by James Cameron) drivers/spi/spi-pxa2xx.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 7e5aab0af501..29e6025f104c 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -1078,6 +1078,20 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *master, pxa2xx_spi_write(drv_data, SSTO, chip->timeout); } + if (drv_data->ssp_type == MMP2_SSP) { + u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR) + & SSSR_TFL_MASK) >> 8; + + if (tx_level) { + /* On MMP2, flipping SSE doesn't to empty TXFIFO. */ + dev_warn(&spi->dev, "%d bytes of garbage in TXFIFO!\n", + tx_level); + if (tx_level > transfer->len) + tx_level = transfer->len; + drv_data->tx += tx_level; + } + } + if (spi_controller_is_slave(master)) { while (drv_data->write(drv_data)) ;