| Message ID | 20181117181225.10737-3-andrew.smirnov@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCIE support for i.MX8MQ | expand |
On Sat, 2018-11-17 at 10:12 -0800, Andrey Smirnov wrote: > PCIE PHY IP block on i.MX7D differs from the one used on i.MX6 family, > so none of the code in current implementation of imx6_pcie_reset_phy() > is applicable. Tested on IMX7d, still appears to work. Note that your patches will collide with Stefan Agner's patch, "PCI: imx6: limit DBI register length", which was recently posted. He changed the way the variants are handled. That method would allow some of the IMX7D || IMX8MQ checks to be re-written as imx6_pcie->drvdata->boolean_attribute Where the attribute can be set in a table and be re-used in every place it comes into play and updated for new devices in one spot, instead of keeping piles of this version or that version or this other version checks up to date.
On Mon, Nov 19, 2018 at 5:22 PM Trent Piepho <tpiepho@impinj.com> wrote: > > On Sat, 2018-11-17 at 10:12 -0800, Andrey Smirnov wrote: > > PCIE PHY IP block on i.MX7D differs from the one used on i.MX6 family, > > so none of the code in current implementation of imx6_pcie_reset_phy() > > is applicable. > > Tested on IMX7d, still appears to work. > Thanks for testing! Unless you object, I'll add your Tested-by tag to this patch. > Note that your patches will collide with Stefan Agner's patch, "PCI: > imx6: limit DBI register length", which was recently posted. > > He changed the way the variants are handled. That method would allow > some of the IMX7D || IMX8MQ checks to be re-written as > > imx6_pcie->drvdata->boolean_attribute > > Where the attribute can be set in a table and be re-used in every place > it comes into play and updated for new devices in one spot, instead of > keeping piles of this version or that version or this other version > checks up to date. Thanks for the heads up! I am expecting that I'd have to re-base this series on "next" in PCI tree before it can be applied. This should provide for a good opportunity to discover and resolve all of the conflicts, I think. Thanks, Andrey Smirnov
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index c140f7987598..3c3002861d25 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -245,6 +245,9 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) { u32 tmp; + if (imx6_pcie->variant == IMX7D) + return; + pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
PCIE PHY IP block on i.MX7D differs from the one used on i.MX6 family, so none of the code in current implementation of imx6_pcie_reset_phy() is applicable. Cc: bhelgaas@google.com Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> --- drivers/pci/controller/dwc/pci-imx6.c | 3 +++ 1 file changed, 3 insertions(+)