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[2003:dc:d732:f500:597d:16a6:3157:3221]) by smtp.googlemail.com with ESMTPSA id g198sm11495337wmd.23.2018.11.23.11.53.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Nov 2018 11:53:29 -0800 (PST) From: Martin Blumenstingl To: carlo@caione.org, khilman@baylibre.com, linux-amlogic@lists.infradead.org Subject: [PATCH 5/6] ARM: dts: meson8b: add the ARM TWD timer Date: Fri, 23 Nov 2018 20:53:10 +0100 Message-Id: <20181123195311.4578-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181123195311.4578-1-martin.blumenstingl@googlemail.com> References: <20181123195311.4578-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181123_115342_345467_9C7665F4 X-CRM114-Status: GOOD ( 10.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Meson8B SoC is using four ARM Cortex-A5 cores which come with a "TWD" (Timer-Watchdog) based timer. This adds support for the ARM TWD Timer on this SoC. Suggested-by: Carlo Caione [ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured" message during boot, use pre-processor macros to specify the IRQ, added the correct clock, dropped TWD watchdog node since there's no driver for it anymore ] Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8b.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 6b097ab8637f..a3a5649e32fa 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -349,6 +349,13 @@ compatible = "arm,cortex-a5-scu"; reg = <0x0 0x100>; }; + + timer@600 { + compatible = "arm,cortex-a5-twd-timer"; + reg = <0x600 0x20>; + interrupts = ; + clocks = <&clkc CLKID_PERIPH>; + }; }; &pwm_ab {