| Message ID | 20181203195856.1886-1-jernej.skrabec@siol.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: sunxi-ng: h3: Allow parent change for ve clock | expand |
On Mon, Dec 03, 2018 at 08:58:56PM +0100, Jernej Skrabec wrote: > Cedrus driver wants to set VE clock higher than it's possible without > changing parent rate. > > In order to correct that, allow changing parent rate for VE clock. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Applied, thanks! Maxime
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index eb5c608428fa..e52155770f39 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c @@ -481,7 +481,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 0x134, 0, 5, 8, 3, BIT(15), 0); static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", - 0x13c, 16, 3, BIT(31), 0); + 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 0x140, BIT(31), CLK_SET_RATE_PARENT);
Cedrus driver wants to set VE clock higher than it's possible without changing parent rate. In order to correct that, allow changing parent rate for VE clock. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> --- drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)