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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id o8sm55023141pfa.42.2018.12.05.23.31.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 05 Dec 2018 23:31:45 -0800 (PST) From: Andrey Smirnov To: Marc Zyngier Subject: [PATCH 2/5] irqchip/irq-imx-gpcv2: Share reg offset calculation code Date: Wed, 5 Dec 2018 23:31:22 -0800 Message-Id: <20181206073125.7255-3-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181206073125.7255-1-andrew.smirnov@gmail.com> References: <20181206073125.7255-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181205_233157_794449_94E44447 X-CRM114-Status: GOOD ( 15.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "A.s. Dong" , Richard Zhu , Jason Cooper , linux-arm-kernel@lists.infradead.org, Andrey Smirnov , linux-kernel@vger.kernel.org, linux-imx@nxp.com, Thomas Gleixner , Leonard Crestez , cphealy@gmail.com, l.stach@pengutronix.de Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Move identical offset calculation code into a small helper function and make use of it in the rest of the code. Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach --- drivers/irqchip/irq-imx-gpcv2.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c index cbed00319315..b262ba8b2652 100644 --- a/drivers/irqchip/irq-imx-gpcv2.c +++ b/drivers/irqchip/irq-imx-gpcv2.c @@ -28,6 +28,11 @@ struct gpcv2_irqchip_data { static struct gpcv2_irqchip_data *imx_gpcv2_instance; +static void __iomem *gpcv2_idx_to_reg(struct gpcv2_irqchip_data *cd, int i) +{ + return cd->gpc_base + cd->cpu2wakeup + i * 4; +} + static int gpcv2_wakeup_source_save(void) { struct gpcv2_irqchip_data *cd; @@ -39,7 +44,7 @@ static int gpcv2_wakeup_source_save(void) return 0; for (i = 0; i < IMR_NUM; i++) { - reg = cd->gpc_base + cd->cpu2wakeup + i * 4; + reg = gpcv2_idx_to_reg(cd, i); cd->saved_irq_mask[i] = readl_relaxed(reg); writel_relaxed(cd->wakeup_sources[i], reg); } @@ -50,17 +55,14 @@ static int gpcv2_wakeup_source_save(void) static void gpcv2_wakeup_source_restore(void) { struct gpcv2_irqchip_data *cd; - void __iomem *reg; int i; cd = imx_gpcv2_instance; if (!cd) return; - for (i = 0; i < IMR_NUM; i++) { - reg = cd->gpc_base + cd->cpu2wakeup + i * 4; - writel_relaxed(cd->saved_irq_mask[i], reg); - } + for (i = 0; i < IMR_NUM; i++) + writel_relaxed(cd->saved_irq_mask[i], gpcv2_idx_to_reg(cd, i)); } static struct syscore_ops imx_gpcv2_syscore_ops = { @@ -97,7 +99,7 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d) u32 val; raw_spin_lock(&cd->rlock); - reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4; + reg = gpcv2_idx_to_reg(cd, d->hwirq / 32); val = readl_relaxed(reg); val &= ~(1 << d->hwirq % 32); writel_relaxed(val, reg); @@ -113,7 +115,7 @@ static void imx_gpcv2_irq_mask(struct irq_data *d) u32 val; raw_spin_lock(&cd->rlock); - reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4; + reg = gpcv2_idx_to_reg(cd, d->hwirq / 32); val = readl_relaxed(reg); val |= 1 << (d->hwirq % 32); writel_relaxed(val, reg);