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Sun, 9 Dec 2018 04:21:31 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Sun, 9 Dec 2018 04:21:31 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wB9ALQ8L007865; Sun, 9 Dec 2018 04:21:29 -0600 From: Vignesh R To: Tero Kristo , Nishanth Menon Subject: [PATCH 1/2] arm64: dts: ti: k3-am654: Add McSPI DT nodes Date: Sun, 9 Dec 2018 15:52:21 +0530 Message-ID: <20181209102222.7624-2-vigneshr@ti.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181209102222.7624-1-vigneshr@ti.com> References: <20181209102222.7624-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181209_022144_189582_3947591C X-CRM114-Status: GOOD ( 12.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Vignesh R Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP There are 3 instances of McSPI in MCU domain and 4 instances in Main domain. Add DT nodes for all McSPI instances present on AM654 SoC. Signed-off-by: Vignesh R --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 52 ++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 30 ++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 0a0a8fc5df64..6c71e67b8988 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -138,4 +138,56 @@ clocks = <&k3_clks 39 0>; clock-names = "fck"; }; + + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x2100000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 137 1>; + power-domains = <&k3_pds 137>; + #address-cells = <1>; + #size-cells = <0>; + }; + + main_spi1: spi@2110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x2110000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 138 1>; + power-domains = <&k3_pds 138>; + #address-cells = <1>; + #size-cells = <0>; + assigned-clocks = <&k3_clks 137 1>; + assigned-clock-rates = <48000000>; + }; + + main_spi2: spi@2120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x2120000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 139 1>; + power-domains = <&k3_pds 139>; + #address-cells = <1>; + #size-cells = <0>; + }; + + main_spi3: spi@2130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x2130000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 140 1>; + power-domains = <&k3_pds 140>; + #address-cells = <1>; + #size-cells = <0>; + }; + + main_spi4: spi@2140000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x2140000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 141 1>; + power-domains = <&k3_pds 141>; + #address-cells = <1>; + #size-cells = <0>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 1fd027748e1f..1aeae52fb239 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -26,4 +26,34 @@ clocks = <&k3_clks 114 1>; power-domains = <&k3_pds 114>; }; + + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x40300000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 142 1>; + power-domains = <&k3_pds 142>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x40310000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 143 1>; + power-domains = <&k3_pds 143>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x0 0x40320000 0x0 0x400>; + interrupts = ; + clocks = <&k3_clks 144 1>; + power-domains = <&k3_pds 144>; + #address-cells = <1>; + #size-cells = <0>; + }; };