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Sun, 9 Dec 2018 04:21:34 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Sun, 9 Dec 2018 04:21:34 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wB9ALQ8M007865; Sun, 9 Dec 2018 04:21:32 -0600 From: Vignesh R To: Tero Kristo , Nishanth Menon Subject: [PATCH 2/2] arm64: dts: ti: k3-am654: Enable main domain McSPI0 Date: Sun, 9 Dec 2018 15:52:22 +0530 Message-ID: <20181209102222.7624-3-vigneshr@ti.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181209102222.7624-1-vigneshr@ti.com> References: <20181209102222.7624-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181209_022142_452001_204DF810 X-CRM114-Status: GOOD ( 13.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rob Herring , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Vignesh R Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Enable McSPI0 of main domain and add DT node for the SPI NOR flash connected to CS0. Signed-off-by: Vignesh R --- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 49ec2c3f5ef1..e41fc3a5987b 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -60,6 +60,15 @@ AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ >; }; + + main_spi0_pins_default: main-spi0-pins-default { + pinctrl-single,pins = < + AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ + AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ + AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */ + AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ + >; + }; }; &main_pmx1 { @@ -136,3 +145,21 @@ pinctrl-names = "default"; pinctrl-0 = <&ecap0_pins_default>; }; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi0_pins_default>; + #address-cells = <1>; + #size-cells= <0>; + ti,pindir-d0-out-d1-in = <1>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + spi-max-frequency = <48000000>; + #address-cells = <1>; + #size-cells= <1>; + }; +};