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DIR:OUT; SFP:1101; SCL:1; SRVR:BN6PR11MB1282; H:BN6PR11MB1842.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: lyuWmiDuJ/aDtrOacE5OudXmy1a9cKez97GOo6aXJINRvA8+9U4+BtwyyxPXsWIy+LQELZhllI58HIgPfabsx+4+Uf/pDx5tgzS//P3Xmor9XmAKaQHRb2fanIBpCqiHfIOU2+WH4rSXcfhqGMZ6xZVgQxF3kAYFQ+39GyvgrIPIb1gQyOsTHyYaJLRNbHkTGHsMgGOJR6B72HMDT8S9q0l0aIUshjfell3lJmu/cKLvOWqLp6ts97MBVrb8mRrrsCFAJ7B96oyVUil0jPe3BuTGgWMULqeay3xmSDc+sJ6US/tehKpX+kLM0tVooENu spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: ec007223-fa55-47f3-3b87-08d65ec31555 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Dec 2018 17:15:29.5039 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB1282 X-OriginatorOrg: microchip.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181210_091546_296884_4873ECCE X-CRM114-Status: GOOD ( 10.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Tudor.Ambarus@microchip.com, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, boris.brezillon@bootlin.com, broonie@kernel.org, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Cyrille Pitchen This patch configures the QSPI0 controller pin muxing and declares a jedec,spi-nor memory. sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash memory which advertises a maximum frequency of 80MHz for Quad IO Fast Read. Set the spi-max-frequency to 80MHz knowing that actually the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz. Signed-off-by: Cyrille Pitchen [tudor.ambarus@microchip.com: - drop partitions, - add spi-rx/tx-bus-width - change spi-max-frequency to match the 80MHz limit advertised by MX25L25673G for Quad IO Fast Read, - reword commit message and subject.] Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/at91-sama5d2_xplained.dts | 31 +++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 518e2b095ccf..171bc82cfbbf 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -108,6 +108,21 @@ }; apb { + qspi0: spi@f0020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0_default>; + /* status = "okay"; */ /* conflict with sdmmc1 */ + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; + }; + spi0: spi@f8000000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; @@ -485,6 +500,22 @@ bias-disable; }; + pinctrl_qspi0_default: qspi0_default { + sck_cs { + pinmux = , + ; + bias-disable; + }; + + data { + pinmux = , + , + , + ; + bias-pull-up; + }; + }; + pinctrl_sdmmc0_default: sdmmc0_default { cmd_data { pinmux = ,