From patchwork Tue Dec 18 09:12:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 10735163 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 56D316C2 for ; Tue, 18 Dec 2018 09:13:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 466562A71F for ; Tue, 18 Dec 2018 09:13:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3A2572A724; Tue, 18 Dec 2018 09:13:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 271542A71F for ; Tue, 18 Dec 2018 09:13:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vW1EUDfK59EvYqmqPI3OmH+1fhh002+lq7Bj49fKBH0=; b=pb0f0Bz38Sn8C2 oGXUOzpYD+XO2acxFlJg870Mdlz7tvSbuepUBOwg8PAj2q7v3SecS13JpC/80OLwc4tJqJD0T5rz0 sO2T8W27RYib6yvzMSP6tQwE6gEznNnn4luEMRGUDoq+s/u4FypcBL+na1/aC7Ymlew3VTKCz0Is0 GGo3XkuTDHI5cgjr1kGyX3nJu7iQGaCK9RYw8NcrDkCcfMnQRpOf8Cs8gz9Iw/erUc9yUs9mkZFkF GWNO6oIKJtdlJ5trsKgWGGuDqC9hLaORBCNqsdtifw4g1E2WCuiPhM7L0AZRKEF/M0YYk+F6HQuGM hhumvyhOoAUcCYx+iTZA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gZBR1-0004e7-2H; Tue, 18 Dec 2018 09:13:03 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gZBQx-0004cv-DT for linux-arm-kernel@lists.infradead.org; Tue, 18 Dec 2018 09:13:00 +0000 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Dec 2018 01:12:47 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 18 Dec 2018 01:12:52 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 18 Dec 2018 01:12:52 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 18 Dec 2018 09:12:52 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 18 Dec 2018 09:12:52 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 18 Dec 2018 01:12:51 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter Subject: [PATCH V3 02/20] dt-bindings: clock: tegra124-dfll: add Tegra210 support Date: Tue, 18 Dec 2018 17:12:14 +0800 Message-ID: <20181218091232.23532-3-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20181218091232.23532-1-josephl@nvidia.com> References: <20181218091232.23532-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1545124367; bh=AQnLTX2e1Oi9iHUJGbPa5+L3Mn7ZKyIGYfnd03JrXcE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=dRgFddZMTUW8Lh41CNq9nrOQUvC5na5aI8S0efHRZx277YX8nJdVQdqI2yJap/LmF TiP1kEg2p39AF3otq/o5M2SqOuvYtFeC8f6X2vvugw6J5HvI1Z1/Tthq+3Mqz1xjY6 J1LrS6VPj36WipSugGdwgr4tuxC7+r7nc8OZjiZC8P8HHr2VMd9uXyT5vmSElrOVpk zReVTxyGp3V09bZgXINpEX2OGncjNv+303qJugnJKpcmlaWyaYmw0Z/v45jT1kyHi2 HUk0fNzY4xMT2mCr5pi008ksYToky7Av2TTa4dHxi5b6+jI282/XmMwtGyR9ErXJCT R7+8Aq9gKZ2ow== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181218_011259_463819_EEBC1B9F X-CRM114-Status: UNSURE ( 8.98 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add Tegra210 support for DFLL clock. Cc: devicetree@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Jon Hunter Reviewed-by: Rob Herring Acked-by: Stephen Boyd --- *V3: - no change *V2: - add ack tag --- .../devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index 38e8cc8c70a8..8a38c8e78acf 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -10,7 +10,9 @@ control module that will automatically adjust the VDD_CPU voltage by communicating with an off-chip PMIC either via an I2C bus or via PWM signals. Required properties: -- compatible : should be "nvidia,tegra124-dfll" +- compatible : should be one of: + - "nvidia,tegra124-dfll": for Tegra124 + - "nvidia,tegra210-dfll": for Tegra210 - reg : Defines the following set of registers, in the order listed: - registers for the DFLL control logic. - registers for the I2C output logic.