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[73.69.118.222]) by smtp.gmail.com with ESMTPSA id m41sm17874920qtc.58.2018.12.26.08.45.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Dec 2018 08:45:12 -0800 (PST) From: Pavel Tatashin To: catalin.marinas@arm.com, will.deacon@arm.com, akpm@linux-foundation.org, rppt@linux.vnet.ibm.com, mhocko@suse.com, ard.biesheuvel@linaro.org, andrew.murray@arm.com, james.morse@arm.com, marc.zyngier@arm.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, pasha.tatashin@soleen.com Subject: [PATCH v3 1/3] arm_arch_timer: add macro for timer nbits Date: Wed, 26 Dec 2018 11:45:07 -0500 Message-Id: <20181226164509.22916-2-pasha.tatashin@soleen.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20181226164509.22916-1-pasha.tatashin@soleen.com> References: <20181226164509.22916-1-pasha.tatashin@soleen.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181226_084524_577422_A72CC6B1 X-CRM114-Status: GOOD ( 12.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The minimum value of bits arm defines for timer value is 56bits, add a new macro ARCH_TIMER_NBITS to use it in code instead of hardcoding 56. Signed-off-by: Pavel Tatashin --- drivers/clocksource/arm_arch_timer.c | 8 ++++---- include/clocksource/arm_arch_timer.h | 3 +++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 9a7d4dc00b6e..e4843ad48bd3 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -175,13 +175,13 @@ static struct clocksource clocksource_counter = { .name = "arch_sys_counter", .rating = 400, .read = arch_counter_read, - .mask = CLOCKSOURCE_MASK(56), + .mask = CLOCKSOURCE_MASK(ARCH_TIMER_NBITS), .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; static struct cyclecounter cyclecounter __ro_after_init = { .read = arch_counter_read_cc, - .mask = CLOCKSOURCE_MASK(56), + .mask = CLOCKSOURCE_MASK(ARCH_TIMER_NBITS), }; struct ate_acpi_oem_info { @@ -963,8 +963,8 @@ static void __init arch_counter_register(unsigned type) timecounter_init(&arch_timer_kvm_info.timecounter, &cyclecounter, start_count); - /* 56 bits minimum, so we assume worst case rollover */ - sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate); + sched_clock_register(arch_timer_read_counter, ARCH_TIMER_NBITS, + arch_timer_rate); } static void arch_timer_stop(struct clock_event_device *clk) diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h index 349e5957c949..c485512e1d01 100644 --- a/include/clocksource/arm_arch_timer.h +++ b/include/clocksource/arm_arch_timer.h @@ -71,6 +71,9 @@ enum arch_timer_spi_nr { #define ARCH_TIMER_EVT_STREAM_FREQ \ (USEC_PER_SEC / ARCH_TIMER_EVT_STREAM_PERIOD_US) +/* 56 bits minimum, so we assume worst case rollover */ +#define ARCH_TIMER_NBITS 56 + struct arch_timer_kvm_info { struct timecounter timecounter; int virtual_irq;