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Thu, 03 Jan 2019 19:07:20 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter Subject: [PATCH V4 05/20] clk: tegra: dfll: registration for multiple SoCs Date: Fri, 4 Jan 2019 11:06:47 +0800 Message-ID: <20190104030702.8684-6-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190104030702.8684-1-josephl@nvidia.com> References: <20190104030702.8684-1-josephl@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1546571227; bh=+I5R+vt1RctPNQ/lHbSOl45ehRPZgqudDxFi+bhS2CQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=rb5lKfKBK0XgjQ+gvk3uHnq2gQ/x1CF9ez2sfDFKNXrUtfPrXK+JZCutAiAp0o9sW Gqi1W/Wt4jpzkGfO9l799JmhZLYqdHkAQhYFa9wX8BBW+sol8wJIQBeSAV8t2j6vVe sGadOUwwJXqAXnvt/QHpy0FfRRcJE2BWP+c5H1R5T8qsCbUPKsEeTaqNMQjVao2qZs uHr2bMU3dval75RByEjPwy8L6AxJ0h4qTmaq3ZGvBWLsiSEyalyMIiK6Kk5yfc5USr miWm2SbRLgeGyeZiRlK66KV72C7qTZ38V2sravCNmdlAQhYz0J10CXaSRLxeuNUYk+ qgFMUnQ/nuSEQ== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190103_190722_643842_79F7A8C8 X-CRM114-Status: GOOD ( 12.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Peter De Schrijver In a future patch, support for the DFLL in Tegra210 will be introduced. This requires support for more than 1 set of CVB and CPU max frequency tables. Signed-off-by: Peter De Schrijver Signed-off-by: Joseph Lo Acked-by: Jon Hunter Acked-by: Stephen Boyd --- *V4: - add ack tag *V3: - no change *V2: - add ack tag --- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 45 ++++++++++++++++------ 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index 269d3595758b..2bf6a769e5ce 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -1,7 +1,7 @@ /* * Tegra124 DFLL FCPU clock source driver * - * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved. + * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved. * * Aleksandr Frid * Paul Walmsley @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -28,8 +29,15 @@ #include "clk-dfll.h" #include "cvb.h" +struct dfll_fcpu_data { + const unsigned long *cpu_max_freq_table; + unsigned int cpu_max_freq_table_size; + const struct cvb_table *cpu_cvb_tables; + unsigned int cpu_cvb_tables_size; +}; + /* Maximum CPU frequency, indexed by CPU speedo id */ -static const unsigned long cpu_max_freq_table[] = { +static const unsigned long tegra124_cpu_max_freq_table[] = { [0] = 2014500000UL, [1] = 2320500000UL, [2] = 2116500000UL, @@ -82,16 +90,36 @@ static const struct cvb_table tegra124_cpu_cvb_tables[] = { }, }; +static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = { + .cpu_max_freq_table = tegra124_cpu_max_freq_table, + .cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table), + .cpu_cvb_tables = tegra124_cpu_cvb_tables, + .cpu_cvb_tables_size = ARRAY_SIZE(tegra124_cpu_cvb_tables) +}; + +static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { + { + .compatible = "nvidia,tegra124-dfll", + .data = &tegra124_dfll_fcpu_data, + }, + { }, +}; + static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) { int process_id, speedo_id, speedo_value, err; struct tegra_dfll_soc_data *soc; + const struct dfll_fcpu_data *fcpu_data; + + fcpu_data = of_device_get_match_data(&pdev->dev); + if (!fcpu_data) + return -ENODEV; process_id = tegra_sku_info.cpu_process_id; speedo_id = tegra_sku_info.cpu_speedo_id; speedo_value = tegra_sku_info.cpu_speedo_value; - if (speedo_id >= ARRAY_SIZE(cpu_max_freq_table)) { + if (speedo_id >= fcpu_data->cpu_max_freq_table_size) { dev_err(&pdev->dev, "unknown max CPU freq for speedo_id=%d\n", speedo_id); return -ENODEV; @@ -107,10 +135,10 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev) return -ENODEV; } - soc->max_freq = cpu_max_freq_table[speedo_id]; + soc->max_freq = fcpu_data->cpu_max_freq_table[speedo_id]; - soc->cvb = tegra_cvb_add_opp_table(soc->dev, tegra124_cpu_cvb_tables, - ARRAY_SIZE(tegra124_cpu_cvb_tables), + soc->cvb = tegra_cvb_add_opp_table(soc->dev, fcpu_data->cpu_cvb_tables, + fcpu_data->cpu_cvb_tables_size, process_id, speedo_id, speedo_value, soc->max_freq); if (IS_ERR(soc->cvb)) { @@ -142,11 +170,6 @@ static int tegra124_dfll_fcpu_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id tegra124_dfll_fcpu_of_match[] = { - { .compatible = "nvidia,tegra124-dfll", }, - { }, -}; - static const struct dev_pm_ops tegra124_dfll_pm_ops = { SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend, tegra_dfll_runtime_resume, NULL)