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[24.22.235.96]) by smtp.gmail.com with ESMTPSA id i193sm100699632pgc.22.2019.01.04.09.50.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 04 Jan 2019 09:50:12 -0800 (PST) From: Andrey Smirnov To: linux-pci@vger.kernel.org Subject: [PATCH v2 17/20] PCI: imx6: Simplify bit operations in imx6_setup_phy_mpll() Date: Fri, 4 Jan 2019 09:49:22 -0800 Message-Id: <20190104174925.17153-18-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190104174925.17153-1-andrew.smirnov@gmail.com> References: <20190104174925.17153-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190104_095014_657560_1EB44A98 X-CRM114-Status: GOOD ( 11.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "A.s. Dong" , Lorenzo Pieralisi , Richard Zhu , linux-arm-kernel@lists.infradead.org, Andrey Smirnov , linux-kernel@vger.kernel.org, Fabio Estevam , linux-imx@nxp.com, Bjorn Helgaas , Leonard Crestez , Chris Healy , Lucas Stach Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Simplify bit operations in imx6_setup_phy_mpll() by using GENMASK/FIELD_PREP. No functional change intended. Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Signed-off-by: Andrey Smirnov --- drivers/pci/controller/dwc/pci-imx6.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 130f577670c8..d8aef9da476f 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -113,12 +113,10 @@ struct imx6_pcie { /* PHY registers (not memory-mapped) */ #define PCIE_PHY_ATEOVRD 0x10 #define PCIE_PHY_ATEOVRD_EN BIT(2) -#define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0 -#define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1 +#define PCIE_PHY_ATEOVRD_REF_CLKDIV BIT(0) #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11 -#define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2 -#define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f +#define PCIE_PHY_MPLL_MULTIPLIER GENMASK(8, 2) #define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9) #define PHY_RX_OVRD_IN_LO 0x1005 @@ -641,16 +639,14 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) } pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); - val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << - PCIE_PHY_MPLL_MULTIPLIER_SHIFT); - val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; + val &= ~PCIE_PHY_MPLL_MULTIPLIER; + val |= FIELD_PREP(PCIE_PHY_MPLL_MULTIPLIER, mult); val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); - val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << - PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); - val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; + val &= ~PCIE_PHY_ATEOVRD_REF_CLKDIV; + val |= FIELD_PREP(PCIE_PHY_ATEOVRD_REF_CLKDIV, div); val |= PCIE_PHY_ATEOVRD_EN; pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);