| Message ID | 20190118135907.2336-2-stefan@agner.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] ARM: dts: imx6q: add pmu interrupt-affinity | expand |
diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts b/arch/arm/boot/dts/imx6dl-tx6s-8034.dts index 9eb2ef17339c..f1606f63d687 100644 --- a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts +++ b/arch/arm/boot/dts/imx6dl-tx6s-8034.dts @@ -68,3 +68,7 @@ MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ >; }; + +&pmu { + interrupt-affinity = <&{/cpus/cpu@0}>; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts b/arch/arm/boot/dts/imx6dl-tx6s-8035.dts index a5532ecc18c5..b3bf1f80aff0 100644 --- a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts +++ b/arch/arm/boot/dts/imx6dl-tx6s-8035.dts @@ -84,3 +84,7 @@ >; }; }; + +&pmu { + interrupt-affinity = <&{/cpus/cpu@0}>; +}; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index f0607eb41df4..3c8b533b3039 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -386,6 +386,11 @@ <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ }; +&pmu { + interrupt-affinity = <&{/cpus/cpu@0}>, + <&{/cpus/cpu@1}>; +}; + &vpu { compatible = "fsl,imx6dl-vpu", "cnm,coda960"; };
Explicitly specify interrupt affinity to avoid HW perfevents need to guess. This avoids the following error upon boot: hw perfevents: no interrupt-affinity property for /pmu, guessing. Specifying all four CPUs shows no aversive effects on i.MX 6Solo SoCs. Signed-off-by: Stefan Agner <stefan@agner.ch> --- arch/arm/boot/dts/imx6dl-tx6s-8034.dts | 4 ++++ arch/arm/boot/dts/imx6dl-tx6s-8035.dts | 4 ++++ arch/arm/boot/dts/imx6dl.dtsi | 5 +++++ 3 files changed, 13 insertions(+)