| Message ID | 20190122073232.7240-1-plaes@plaes.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/sun4i: hdmi: Fix usage of TMDS clock | expand |
On Tue, Jan 22, 2019 at 09:32:32AM +0200, Priit Laes wrote: > From: Priit Laes <priit.laes@paf.com> > > Although TMDS clock is required for HDMI to properly function, > nobody called clk_prepare_enable(). This fixes reference counting > issues and makes sure clock is running when it needs to be running. > > Due to TDMS clock being parent clock for DDC clock, TDMS clock > was turned on/off for each EDID probe, causing spurious failures > for certain HDMI/DVI screens. > > Fixes: 9c5681011a0c ("drm/sun4i: Add HDMI support") > > Signed-off-by: Priit Laes <priit.laes@paf.com> > --- > drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c > index 061d2e0d9011..25f4d676fd82 100644 > --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c > +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c > @@ -92,6 +92,8 @@ static void sun4i_hdmi_disable(struct drm_encoder *encoder) > val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); > val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; > writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); > + > + clk_disable_unprepare(hdmi->tmds_clk); > } > > static void sun4i_hdmi_enable(struct drm_encoder *encoder) > @@ -112,6 +114,8 @@ static void sun4i_hdmi_enable(struct drm_encoder *encoder) > val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; > > writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); > + > + clk_prepare_enable(hdmi->tmds_clk); We'll probably need to enable that clock to send the infoframes as well. I moved it earlier (and that allows the enable and disable function to be symetric as well). Thanks for figuring this out! Maxime
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c index 061d2e0d9011..25f4d676fd82 100644 --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c @@ -92,6 +92,8 @@ static void sun4i_hdmi_disable(struct drm_encoder *encoder) val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); + + clk_disable_unprepare(hdmi->tmds_clk); } static void sun4i_hdmi_enable(struct drm_encoder *encoder) @@ -112,6 +114,8 @@ static void sun4i_hdmi_enable(struct drm_encoder *encoder) val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); + + clk_prepare_enable(hdmi->tmds_clk); } static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,