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Fri, 25 Jan 2019 02:55:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akkea.ca; s=mail; t=1548384937; bh=+JXGIVucnYCY0cluddvyVeHVzItz/VTc2jupzPlE5mk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=S/T368i0EE27Nh6XHcxhO1cbGHBeLDfxuHZ5N8hx6l+DAEHXkNUG6vShI91PFEH7c fY2Q6hN0bu9dtF7QyKs+brb281XIiCsHYKwnp6xT7gLLuVOupR6Bb0GjzZnF1WjIQ/ CLbrNz2JEkVOPgIILCjns859Z4HZn2A+GGi1/Tcw= From: "Angus Ainslie (Purism)" To: angus@akkea.ca Subject: [PATCH v4 1/5] dmaengine: imx-sdma: add clock ratio 1:1 check Date: Thu, 24 Jan 2019 19:55:24 -0700 Message-Id: <20190125025528.15645-2-angus@akkea.ca> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190125025528.15645-1-angus@akkea.ca> References: <20190120023150.17138-1-angus@akkea.ca> <20190125025528.15645-1-angus@akkea.ca> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190124_185538_563642_78F0BA4D X-CRM114-Status: GOOD ( 10.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Baluta , linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, Vinod Koul , NXP Linux Team , Pengutronix Kernel Team , angus.ainslie@puri.sm, linux-arm-kernel@lists.infradead.org, Lucas Stach MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On i.mx8 mscale B0 chip, AHB/SDMA clock ratio 2:1 can't be supportted, since SDMA clock ratio has to be increased to 250Mhz, AHB can't reach to 500Mhz, so use 1:1 instead. Based on NXP commit MLK-16841-1 by Robin Gong Signed-off-by: Angus Ainslie (Purism) --- drivers/dma/imx-sdma.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index 0b3a67ff8e82..5e5ef0b5a973 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -440,6 +440,8 @@ struct sdma_engine { unsigned int irq; dma_addr_t bd0_phys; struct sdma_buffer_descriptor *bd0; + /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/ + bool clk_ratio; }; static int sdma_config_write(struct dma_chan *chan, @@ -662,8 +664,14 @@ static int sdma_run_channel0(struct sdma_engine *sdma) dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); /* Set bits of CONFIG register with dynamic context switching */ - if (readl(sdma->regs + SDMA_H_CONFIG) == 0) - writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); + if ((readl(sdma->regs + SDMA_H_CONFIG) & ~SDMA_H_CONFIG_ACR) == 0) { + reg = SDMA_H_CONFIG_CSM; + + if (sdma->clk_ratio) + reg |= SDMA_H_CONFIG_ACR; + + writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); + } return ret; } @@ -1840,6 +1848,9 @@ static int sdma_init(struct sdma_engine *sdma) if (ret) goto disable_clk_ipg; + if (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)) + sdma->clk_ratio = 1; + /* Be sure SDMA has not started yet */ writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); @@ -1880,8 +1891,10 @@ static int sdma_init(struct sdma_engine *sdma) writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); /* Set bits of CONFIG register but with static context switching */ - /* FIXME: Check whether to set ACR bit depending on clock ratios */ - writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); + if (sdma->clk_ratio) + writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); + else + writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);