diff mbox series

[v2,1/2] arm64: dts: fsl: imx8mq: add USB nodes

Message ID 20190125162559.15101-1-l.stach@pengutronix.de (mailing list archive)
State New, archived
Headers show
Series [v2,1/2] arm64: dts: fsl: imx8mq: add USB nodes | expand

Commit Message

Lucas Stach Jan. 25, 2019, 4:25 p.m. UTC 
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
v2: Drop snps,power-down-scale, which isn't supported by upstream
    driver, yet.
---
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 64 +++++++++++++++++++++++
 1 file changed, 64 insertions(+)

Comments

Shawn Guo Feb. 1, 2019, 7:10 a.m. UTC | #1 
On Fri, Jan 25, 2019 at 05:25:58PM +0100, Lucas Stach wrote:
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

Please put something into the commit log for the future patches.  And
it's clear enough for 'arm64: dts: imx8mq: ...' to be the prefix.

Applied both, thanks.

Shawn

> ---
> v2: Drop snps,power-down-scale, which isn't supported by upstream
>     driver, yet.
> ---
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 64 +++++++++++++++++++++++
>  1 file changed, 64 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index af2584d51fa2..51c9e899c35d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -472,6 +472,70 @@
>  			};
>  		};
>  
> +		usb_dwc3_0: usb@38100000 {
> +			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
> +			reg = <0x38100000 0x10000>;
> +			clocks = <&clk IMX8MQ_CLK_USB_BUS>,
> +			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
> +			         <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
> +			clock-names = "bus_early", "ref", "suspend";
> +			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
> +			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
> +			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
> +			                         <&clk IMX8MQ_SYS1_PLL_100M>;
> +			assigned-clock-rates = <500000000>, <100000000>;
> +			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> +			phys = <&usb3_phy0>, <&usb3_phy0>;
> +			phy-names = "usb2-phy", "usb3-phy";
> +			power-domains = <&pgc_otg1>;
> +			usb3-resume-missing-cas;
> +			status = "disabled";
> +		};
> +
> +		usb3_phy0: phy@381f0040 {
> +			compatible = "fsl,imx8mq-usb-phy";
> +			reg = <0x381f0040 0x40>;
> +			clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
> +			clock-names = "phy";
> +			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
> +			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
> +			assigned-clock-rates = <100000000>;
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		usb_dwc3_1: usb@38200000 {
> +			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
> +			reg = <0x38200000 0x10000>;
> +			clocks = <&clk IMX8MQ_CLK_USB_BUS>,
> +			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
> +			         <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
> +			clock-names = "bus_early", "ref", "suspend";
> +			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
> +			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
> +			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
> +			                         <&clk IMX8MQ_SYS1_PLL_100M>;
> +			assigned-clock-rates = <500000000>, <100000000>;
> +			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +			phys = <&usb3_phy1>, <&usb3_phy1>;
> +			phy-names = "usb2-phy", "usb3-phy";
> +			power-domains = <&pgc_otg2>;
> +			usb3-resume-missing-cas;
> +			status = "disabled";
> +		};
> +
> +		usb3_phy1: phy@382f0040 {
> +			compatible = "fsl,imx8mq-usb-phy";
> +			reg = <0x382f0040 0x40>;
> +			clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
> +			clock-names = "phy";
> +			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
> +			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
> +			assigned-clock-rates = <100000000>;
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		gic: interrupt-controller@38800000 {
>  			compatible = "arm,gic-v3";
>  			reg = <0x38800000 0x10000>,	/* GIC Dist */
> -- 
> 2.20.1
>
Shawn Guo Feb. 1, 2019, 7:15 a.m. UTC | #2 
On Fri, Jan 25, 2019 at 05:25:58PM +0100, Lucas Stach wrote:
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> v2: Drop snps,power-down-scale, which isn't supported by upstream
>     driver, yet.
> ---
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 64 +++++++++++++++++++++++
>  1 file changed, 64 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index af2584d51fa2..51c9e899c35d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -472,6 +472,70 @@
>  			};
>  		};
>  
> +		usb_dwc3_0: usb@38100000 {
> +			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
> +			reg = <0x38100000 0x10000>;
> +			clocks = <&clk IMX8MQ_CLK_USB_BUS>,
> +			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
> +			         <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
> +			clock-names = "bus_early", "ref", "suspend";
> +			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
> +			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
> +			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
> +			                         <&clk IMX8MQ_SYS1_PLL_100M>;
> +			assigned-clock-rates = <500000000>, <100000000>;
> +			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> +			phys = <&usb3_phy0>, <&usb3_phy0>;
> +			phy-names = "usb2-phy", "usb3-phy";
> +			power-domains = <&pgc_otg1>;
> +			usb3-resume-missing-cas;
> +			status = "disabled";
> +		};
> +
> +		usb3_phy0: phy@381f0040 {

As per Devicetree Specification, usb-phy is a better node name for it.
I fixed it up.

Shawn

> +			compatible = "fsl,imx8mq-usb-phy";
> +			reg = <0x381f0040 0x40>;
> +			clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
> +			clock-names = "phy";
> +			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
> +			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
> +			assigned-clock-rates = <100000000>;
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		usb_dwc3_1: usb@38200000 {
> +			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
> +			reg = <0x38200000 0x10000>;
> +			clocks = <&clk IMX8MQ_CLK_USB_BUS>,
> +			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
> +			         <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
> +			clock-names = "bus_early", "ref", "suspend";
> +			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
> +			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
> +			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
> +			                         <&clk IMX8MQ_SYS1_PLL_100M>;
> +			assigned-clock-rates = <500000000>, <100000000>;
> +			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> +			phys = <&usb3_phy1>, <&usb3_phy1>;
> +			phy-names = "usb2-phy", "usb3-phy";
> +			power-domains = <&pgc_otg2>;
> +			usb3-resume-missing-cas;
> +			status = "disabled";
> +		};
> +
> +		usb3_phy1: phy@382f0040 {
> +			compatible = "fsl,imx8mq-usb-phy";
> +			reg = <0x382f0040 0x40>;
> +			clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
> +			clock-names = "phy";
> +			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
> +			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
> +			assigned-clock-rates = <100000000>;
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		gic: interrupt-controller@38800000 {
>  			compatible = "arm,gic-v3";
>  			reg = <0x38800000 0x10000>,	/* GIC Dist */
> -- 
> 2.20.1
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index af2584d51fa2..51c9e899c35d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -472,6 +472,70 @@ 
 			};
 		};
 
+		usb_dwc3_0: usb@38100000 {
+			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+			reg = <0x38100000 0x10000>;
+			clocks = <&clk IMX8MQ_CLK_USB_BUS>,
+			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
+			         <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
+			clock-names = "bus_early", "ref", "suspend";
+			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
+			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
+			                         <&clk IMX8MQ_SYS1_PLL_100M>;
+			assigned-clock-rates = <500000000>, <100000000>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usb3_phy0>, <&usb3_phy0>;
+			phy-names = "usb2-phy", "usb3-phy";
+			power-domains = <&pgc_otg1>;
+			usb3-resume-missing-cas;
+			status = "disabled";
+		};
+
+		usb3_phy0: phy@381f0040 {
+			compatible = "fsl,imx8mq-usb-phy";
+			reg = <0x381f0040 0x40>;
+			clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
+			clock-names = "phy";
+			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
+			assigned-clock-rates = <100000000>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usb_dwc3_1: usb@38200000 {
+			compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+			reg = <0x38200000 0x10000>;
+			clocks = <&clk IMX8MQ_CLK_USB_BUS>,
+			         <&clk IMX8MQ_CLK_USB_CORE_REF>,
+			         <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
+			clock-names = "bus_early", "ref", "suspend";
+			assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
+			                  <&clk IMX8MQ_CLK_USB_CORE_REF>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
+			                         <&clk IMX8MQ_SYS1_PLL_100M>;
+			assigned-clock-rates = <500000000>, <100000000>;
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+			phys = <&usb3_phy1>, <&usb3_phy1>;
+			phy-names = "usb2-phy", "usb3-phy";
+			power-domains = <&pgc_otg2>;
+			usb3-resume-missing-cas;
+			status = "disabled";
+		};
+
+		usb3_phy1: phy@382f0040 {
+			compatible = "fsl,imx8mq-usb-phy";
+			reg = <0x382f0040 0x40>;
+			clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
+			clock-names = "phy";
+			assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
+			assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
+			assigned-clock-rates = <100000000>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>,	/* GIC Dist */