Message ID | 20190129080926.36773-16-Zhiqiang.Hou@nxp.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs | expand |
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote: > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > Change the "gpio_slave" and "apb_csr" to optional, the "gpio_slave" > is not used in current code, and "apb_csr" is not used by some > platforms. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > Acked-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> > --- > V3: > - No change > > Documentation/devicetree/bindings/pci/mobiveil-pcie.txt | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > index a618d4787dd7..64156993e052 100644 > --- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt > @@ -10,8 +10,10 @@ Required properties: > interrupt source. The value must be 1. > - compatible: Should contain "mbvl,gpex40-pcie" > - reg: Should contain PCIe registers location and length > + Mandatory: > "config_axi_slave": PCIe controller registers > "csr_axi_slave" : Bridge config registers > + Optional: > "gpio_slave" : GPIO registers to control slot power > "apb_csr" : MSI registers > > -- > 2.17.1 > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
diff --git a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt index a618d4787dd7..64156993e052 100644 --- a/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt +++ b/Documentation/devicetree/bindings/pci/mobiveil-pcie.txt @@ -10,8 +10,10 @@ Required properties: interrupt source. The value must be 1. - compatible: Should contain "mbvl,gpex40-pcie" - reg: Should contain PCIe registers location and length + Mandatory: "config_axi_slave": PCIe controller registers "csr_axi_slave" : Bridge config registers + Optional: "gpio_slave" : GPIO registers to control slot power "apb_csr" : MSI registers