From patchwork Sun Mar 3 17:12:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 10837187 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7FE5214DE for ; Sun, 3 Mar 2019 18:10:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 656FD29BA7 for ; Sun, 3 Mar 2019 18:10:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5640129BB0; Sun, 3 Mar 2019 18:10:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3440B29BA7 for ; Sun, 3 Mar 2019 18:10:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YZbHIbyTnhvBLJ1/cyAVcl8amvKCmycwiwrtnWitQio=; b=f4Y6GRa0zU9+gj hNade3ql1Ow71psk8qywNtEdpR63lLYq8+EbaLgYd+MuzkbgsCW5OfwcYWxPzLc93xFT8qSwe8xwn n5dReiLkvdNO/PYwbC37XUZp4WnE/rbpzn5+vGyoLXaZJcB929yUipaUzFqNykZMAB4Zu6VYhifUN R+gu8CwlQ3f63/GZO9xkWvI2eu/LgE5N8X+pfm9ZiHxC9oShH1yAE0NbwiNzS/IUa/XGourHBQWV4 S/C9roVPR58rVzBU7qnJ/VnA0pfH9hnkbVyRl6Biici5DOvPvsFq2fgc9LXGi+v3aD5vwaaPugehq 2zbVauv3procSjS6H3Ng==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h0VZW-0000yS-Gx; Sun, 03 Mar 2019 18:10:46 +0000 Received: from merlin.infradead.org ([2001:8b0:10b:1231::1]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h0VZU-0000yG-AN for linux-arm-kernel@bombadil.infradead.org; Sun, 03 Mar 2019 18:10:44 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=merlin.20170209; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=buciGHsipdLQFuQo4BFBFhcyxYei+3vIbC+6BJ6jYFQ=; b=TE82O7NW6qq2QOpW0gTXiCk5v2 reiwKpNygC9k4Cdpi/E3ixiPcByqvIvygXMU8SCot19P3QG6DQ7Ysb233zm2m+y1C60GhsfQR9EZs /n4jVEvt6d8Rvd1vdGFr1kHx/H6j3aTbz2Uvrdbf9uLfycrvdOA5SGZz1WN0r1OwDfV8i06vSf7TN tf8K1QkK9u5kMYxMDcmHAWArXaemA5dOnigpiYxlccLG+0G+LBDDTeeT9ni5vdXEvemNsQSc180v4 qxm8WJONSZZqySzVCHM8GIer5l3+2lTgFnsNEiD2OkgbWxf4S5pYETAWbjspDNoSd/gjniHq1HBdJ oKO5qTQQ==; Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]) by merlin.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h0Ugf-0007dA-4O for linux-arm-kernel@lists.infradead.org; Sun, 03 Mar 2019 17:14:06 +0000 Received: by mail-pl1-x642.google.com with SMTP id y5so1348212plk.8 for ; Sun, 03 Mar 2019 09:14:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=buciGHsipdLQFuQo4BFBFhcyxYei+3vIbC+6BJ6jYFQ=; b=Taj43xsj5ircTOgqnLYTo21UaXCH5rYpbmC2ssYt31/Q90ds5shENkdEyDMl3oRPs+ ar2h0QnFUPLLGgTs0vRC0uQ4UrAdbMf3MOC/wBhy/uxuJU7xQrTMgSZEAqgObriqswJO fsKYqMW/noIAGaY9hz0cTUY6r8tbn6Ucf2ZsnP2IMDSW17eoOKR5YZnSF4c7/sGfdMoD q4wzNePj6TUJgsOYcqkVx0yWTefwgwU6bewpZZ6/mqUjMLRGLs/huA3xudyXAktyYh7n WmNQSmTy7hqdOtyce74/Ub+OXEVV5R35CQSKCZj1Jrt6U0oQahPItFvFKLfY98g+qy3o YeDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=buciGHsipdLQFuQo4BFBFhcyxYei+3vIbC+6BJ6jYFQ=; b=J1nRtfd74aujh7D+widw12UsgLg693g1/BXOzQAecpVcQlzHUuSg9uwoyWBGAt3YJC eRqY/iyUp+hml+5u81GahUnfqASBgz88G8fy3NClAt+hb+S8qoMnq+8m0T+6e2xz43Z2 p+FuWHx/ju0m6utuk+LiXJVILZWVqJOSvYcYH62zP4utWR7MZfQRUAh4SvZDTyxlOFIZ Hb1QYLbc6anWvdDNKmoNNDd98KnJzy/4ZzTHW9acYG5PEEkOHEYkVqV1eGI8560J60hR S+yI73sHQ7f+oBteAYWt9fq1d51R6kUWbrl912xUCUNpF02y/UQhXQzukOc1EdA18gKx R0zw== X-Gm-Message-State: APjAAAXrkBqUCz4ohsWh4pHAAPnmf+plOjOUelUTIWzbiT3PkE+A16Yn aG5a4mN0CkXj9k40XcX5Ek4= X-Google-Smtp-Source: APXvYqxdhTjL2GUEPl23GkRtn+9EX4/9c7cliAA2PV7vhrfUNc/v+j1DrdHHCuYlZkfyup+kwuz9KQ== X-Received: by 2002:a17:902:45:: with SMTP id 63mr16286052pla.281.1551633237659; Sun, 03 Mar 2019 09:13:57 -0800 (PST) Received: from localhost.localdomain (ppp91-79-175-49.pppoe.mtu-net.ru. [91.79.175.49]) by smtp.gmail.com with ESMTPSA id e22sm5349412pfi.126.2019.03.03.09.13.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 03 Mar 2019 09:13:57 -0800 (PST) From: Dmitry Osipenko To: Russell King , Thierry Reding , Jonathan Hunter , Robert Yang , =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= Subject: [PATCH v9 5/7] ARM: tegra: Don't apply CPU erratas in insecure mode Date: Sun, 3 Mar 2019 20:12:12 +0300 Message-Id: <20190303171214.24821-6-digetx@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190303171214.24821-1-digetx@gmail.com> References: <20190303171214.24821-1-digetx@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190303_121405_199973_09303AFA X-CRM114-Status: GOOD ( 16.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP CPU isn't allowed to touch secure registers while running under secure monitor. Hence skip applying of CPU erratas in the reset handler if Trusted Foundations firmware presents. Partially based on work done by Michał Mirosław [1]. [1] https://www.spinics.net/lists/arm-kernel/msg594768.html Tested-by: Robert Yang Tested-by: Michał Mirosław Signed-off-by: Michał Mirosław Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/reset-handler.S | 23 ++++++++++++----------- arch/arm/mach-tegra/reset.c | 3 +++ arch/arm/mach-tegra/reset.h | 9 +++++++-- arch/arm/mach-tegra/sleep-tegra20.S | 4 ++++ 4 files changed, 26 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index e22ccf87eded..809fbc200cef 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -29,8 +29,6 @@ #define PMC_SCRATCH41 0x140 -#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) - #ifdef CONFIG_PM_SLEEP /* * tegra_resume @@ -121,6 +119,12 @@ ENTRY(__tegra_cpu_reset_handler) cpsid aif, 0x13 @ SVC mode, interrupts disabled tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 + + adr r12, __tegra_cpu_reset_handler_data + ldr r5, [r12, #RESET_DATA(TF_PRESENT)] + cmp r5, #0 + bne after_errata + #ifdef CONFIG_ARCH_TEGRA_2x_SOC t20_check: cmp r6, #TEGRA20 @@ -155,7 +159,6 @@ after_errata: and r10, r10, #0x3 @ R10 = CPU number mov r11, #1 mov r11, r11, lsl r10 @ R11 = CPU mask - adr r12, __tegra_cpu_reset_handler_data #ifdef CONFIG_SMP /* Does the OS know about this CPU? */ @@ -169,10 +172,9 @@ after_errata: cmp r6, #TEGRA20 bne 1f /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */ - mov32 r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET mov r0, #CPU_NOT_RESETTABLE cmp r10, #0 - strbne r0, [r5, #__tegra20_cpu1_resettable_status_offset] + strbne r0, [r12, #RESET_DATA(RESETTABLE_STATUS)] 1: #endif @@ -277,14 +279,13 @@ ENDPROC(__tegra_cpu_reset_handler) .align L1_CACHE_SHIFT .type __tegra_cpu_reset_handler_data, %object .globl __tegra_cpu_reset_handler_data + .globl __tegra_cpu_reset_handler_data_offset + .equ __tegra_cpu_reset_handler_data_offset, \ + . - __tegra_cpu_reset_handler_start __tegra_cpu_reset_handler_data: - .rept TEGRA_RESET_DATA_SIZE - .long 0 + .rept TEGRA_RESET_DATA_SIZE + .long 0 .endr - .globl __tegra20_cpu1_resettable_status_offset - .equ __tegra20_cpu1_resettable_status_offset, \ - . - __tegra_cpu_reset_handler_start - .byte 0 .align L1_CACHE_SHIFT ENTRY(__tegra_cpu_reset_handler_end) diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index dc558892753c..b02ae7699842 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "iomap.h" #include "irammap.h" @@ -89,6 +90,8 @@ static void __init tegra_cpu_reset_handler_enable(void) void __init tegra_cpu_reset_handler_init(void) { + __tegra_cpu_reset_handler_data[TEGRA_RESET_TF_PRESENT] = + trusted_foundations_registered(); #ifdef CONFIG_SMP __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h index 9c479c7925b8..db0e6b3097ab 100644 --- a/arch/arm/mach-tegra/reset.h +++ b/arch/arm/mach-tegra/reset.h @@ -25,7 +25,11 @@ #define TEGRA_RESET_STARTUP_SECONDARY 3 #define TEGRA_RESET_STARTUP_LP2 4 #define TEGRA_RESET_STARTUP_LP1 5 -#define TEGRA_RESET_DATA_SIZE 6 +#define TEGRA_RESET_RESETTABLE_STATUS 6 +#define TEGRA_RESET_TF_PRESENT 7 +#define TEGRA_RESET_DATA_SIZE 8 + +#define RESET_DATA(x) ((TEGRA_RESET_##x)*4) #ifndef __ASSEMBLY__ @@ -49,7 +53,8 @@ void __tegra_cpu_reset_handler_end(void); (u32)__tegra_cpu_reset_handler_start))) #define tegra20_cpu1_resettable_status \ (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ - (u32)__tegra20_cpu1_resettable_status_offset)) + ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \ + (u32)__tegra_cpu_reset_handler_start))) #endif #define tegra_cpu_reset_handler_offset \ diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S index dedeebfccc55..50d51d3465f6 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -28,6 +28,7 @@ #include #include "irammap.h" +#include "reset.h" #include "sleep.h" #define EMC_CFG 0xc @@ -53,6 +54,9 @@ #define APB_MISC_XM2CFGCPADCTRL2 0x8e4 #define APB_MISC_XM2CFGDPADCTRL2 0x8e8 +#define __tegra20_cpu1_resettable_status_offset \ + (__tegra_cpu_reset_handler_data_offset + RESET_DATA(RESETTABLE_STATUS)) + .macro pll_enable, rd, r_car_base, pll_base ldr \rd, [\r_car_base, #\pll_base] tst \rd, #(1 << 30)