From patchwork Tue Mar 5 05:05:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 10838981 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D5AE11823 for ; Tue, 5 Mar 2019 05:06:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BF6AA2A872 for ; Tue, 5 Mar 2019 05:06:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B021D2B296; Tue, 5 Mar 2019 05:06:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4BD242B296 for ; Tue, 5 Mar 2019 05:06:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=esKn+tHnaB0fKJndkB/Hx4I4On7Co+of617uONsY8P0=; b=kZtNtNebXeBuup 9xiiXE1i6FDG5tY5XDVpxbNaU1ErPc8v+lnND8hViNOq+0MJgkCPCiEkp0wQKWY0bkTRx/A6uRXi5 Nb/QqNt67m9R8XS1TSktcWX8D5zvbgA1HvC11P9Klokz2gcZAqMGQAaozC533oM8FZsPI6hnth0IA dXHHnk5lGsY30hnT0iRzk6TdDYZh/PphwWCazPmCmR4dM6Y39ruYu6zv+TadOTQiBHvtw539SfuRF Q/NeJHnReUNIQ4STtGdJltf3BntsHt5wJPdbS4u8QvFgDjUsue6twENMqz8mzGGqHUzRA6t1cev6c rcab3Y/YeWuyL0LdJliw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h12Hg-0000dB-OT; Tue, 05 Mar 2019 05:06:32 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h12HL-00005Y-As; Tue, 05 Mar 2019 05:06:15 +0000 X-UUID: 704b5eb9060e46adb178ef32a4c3901f-20190304 X-UUID: 704b5eb9060e46adb178ef32a4c3901f-20190304 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 685940760; Mon, 04 Mar 2019 21:05:58 -0800 Received: from mtkmbs03n2.mediatek.inc (172.21.101.182) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 4 Mar 2019 21:05:57 -0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs03n2.mediatek.inc (172.21.101.182) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 5 Mar 2019 13:05:55 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 5 Mar 2019 13:05:55 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Stephen Boyd , Rob Herring Subject: [PATCH v5 9/9] clk: mediatek: Allow changing PLL rate when it is off Date: Tue, 5 Mar 2019 13:05:46 +0800 Message-ID: <20190305050546.23431-11-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190305050546.23431-1-weiyi.lu@mediatek.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 104CB3A5F888D3C353C3151EF2B2F2C9E12C8E12A49C6AB5DD017CD1D5FD3D3E2000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190304_210611_595641_6970C024 X-CRM114-Status: GOOD ( 10.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: James Liao Some modules may need to change its clock rate before turn on it. So changing PLL's rate when it is off should be allowed. This patch removes PLL enabled check before set rate, so that PLLs can set new frequency even if they are off. On MT8173 for example, ARMPLL's enable bit can be controlled by other HW. That means ARMPLL may be turned on even if we (CPU / SW) set ARMPLL's enable bit as 0. In this case, SW may want and can still change ARMPLL's rate by changing its pcw and postdiv settings. But without this patch, new pcw setting will not be applied because its enable bit is 0. Signed-off-by: James Liao Acked-by: Michael Turquette Signed-off-by: Weiyi Lu Reviewed-by: James Liao --- drivers/clk/mediatek/clk-pll.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 65cee1d6c400..8d556fc99fed 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -124,9 +124,6 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, int postdiv) { u32 chg, val; - int pll_en; - - pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; /* disable tuner */ __mtk_pll_tuner_disable(pll); @@ -147,12 +144,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, pll->data->pcw_shift); val |= pcw << pll->data->pcw_shift; writel(val, pll->pcw_addr); - - chg = readl(pll->pcw_chg_addr); - - if (pll_en) - chg |= PCW_CHG_MASK; - + chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; writel(chg, pll->pcw_chg_addr); if (pll->tuner_addr) writel(val + 1, pll->tuner_addr); @@ -160,8 +152,7 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, /* restore tuner_en */ __mtk_pll_tuner_enable(pll); - if (pll_en) - udelay(20); + udelay(20); } /*