From patchwork Tue Mar 5 05:05:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 10838973 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ABFF417E0 for ; Tue, 5 Mar 2019 05:06:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 967AD2A872 for ; Tue, 5 Mar 2019 05:06:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8AC3B2B29C; Tue, 5 Mar 2019 05:06:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2943A2A872 for ; Tue, 5 Mar 2019 05:06:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=INa/N0Ze08+spXbXOen2a3+66pH/dUacV0yfT8cI3bw=; b=LJxO1OZpEAKUoy ad1ZHrs1ZphOdQF9eaiqraPFFYBJPUM7j2L3aoMynF3FJYes7NDz2VMk0hOCAyYoU4OLO//mXgKk6 1kLLbZ9ddCBy+kAM2ix6HAEYWSWYpuWlEO/qnA1ANxLTusdYPMS7+WnSqLgQ3uZWpLaBqNUzxktYD 89IbtPblSn6lkgGm+d+Pkqh+t+3cYUjcBWXcrJmqoAQxm4NMpDcXrwOcdGFZ1/VQqAVSBAUMJHBuR row3i1L+QSQykPP1y+j/QoNu9e8k0/ZfMUPeZN+TD6SbblzCYaGLWovt4UWQLaNKcbJyO2QcKDXyG 56TBaIK7Jl5ZEISN/Gzg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h12HP-0000A6-2I; Tue, 05 Mar 2019 05:06:15 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h12HF-0008Sc-R2; Tue, 05 Mar 2019 05:06:07 +0000 X-UUID: 5520f85d16914f84804a5965cdf08bc7-20190304 X-UUID: 5520f85d16914f84804a5965cdf08bc7-20190304 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 1096445623; Mon, 04 Mar 2019 21:05:59 -0800 Received: from MTKMBS02N2.mediatek.inc (172.21.101.101) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 4 Mar 2019 21:05:57 -0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 5 Mar 2019 13:05:55 +0800 Received: from mtkslt210.mediatek.inc (10.21.14.14) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 5 Mar 2019 13:05:55 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Stephen Boyd , Rob Herring Subject: [PATCH v5 7/9] clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data Date: Tue, 5 Mar 2019 13:05:44 +0800 Message-ID: <20190305050546.23431-9-weiyi.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190305050546.23431-1-weiyi.lu@mediatek.com> References: <20190305050546.23431-1-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: A427876116C948A4DDBDA531EEA06691223D362E671A29201BA8EDB6E0A0F2A72000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190304_210605_882271_C622E84E X-CRM114-Status: GOOD ( 12.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In previous MediaTek PLL design, it assumes the pcw change control is always on the CON1 register. However, the pcw change bit on MT8183 was moved onto CON0 because the the PCW length of audio PLLs are extended to 32-bit. Add configurable pcw_chg_reg to set the pcw change control register address or using the default control register CON1 if without setting in pll data. Signed-off-by: Weiyi Lu Reviewed-by: James Liao --- drivers/clk/mediatek/clk-mtk.h | 1 + drivers/clk/mediatek/clk-pll.c | 17 +++++++++++------ 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 928905496c4b..37ae944548e9 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -221,6 +221,7 @@ struct mtk_pll_data { int pcwibits; uint32_t pcw_reg; int pcw_shift; + uint32_t pcw_chg_reg; const struct mtk_pll_div_table *div_table; const char *parent_name; }; diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 67aaa3082d9b..65cee1d6c400 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -27,7 +27,7 @@ #define CON0_BASE_EN BIT(0) #define CON0_PWR_ON BIT(0) #define CON0_ISO_EN BIT(1) -#define CON0_PCW_CHG BIT(31) +#define PCW_CHG_MASK BIT(31) #define AUDPLL_TUNER_EN BIT(31) @@ -51,6 +51,7 @@ struct mtk_clk_pll { void __iomem *tuner_addr; void __iomem *tuner_en_addr; void __iomem *pcw_addr; + void __iomem *pcw_chg_addr; const struct mtk_pll_data *data; }; @@ -122,7 +123,7 @@ static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll) static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, int postdiv) { - u32 con1, val; + u32 chg, val; int pll_en; pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN; @@ -147,14 +148,14 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, val |= pcw << pll->data->pcw_shift; writel(val, pll->pcw_addr); - con1 = readl(pll->base_addr + REG_CON1); + chg = readl(pll->pcw_chg_addr); if (pll_en) - con1 |= CON0_PCW_CHG; + chg |= PCW_CHG_MASK; - writel(con1, pll->base_addr + REG_CON1); + writel(chg, pll->pcw_chg_addr); if (pll->tuner_addr) - writel(con1 + 1, pll->tuner_addr); + writel(val + 1, pll->tuner_addr); /* restore tuner_en */ __mtk_pll_tuner_enable(pll); @@ -329,6 +330,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, pll->pwr_addr = base + data->pwr_reg; pll->pd_addr = base + data->pd_reg; pll->pcw_addr = base + data->pcw_reg; + if (data->pcw_chg_reg) + pll->pcw_chg_addr = base + data->pcw_chg_reg; + else + pll->pcw_chg_addr = pll->base_addr + REG_CON1; if (data->tuner_reg) pll->tuner_addr = base + data->tuner_reg; if (data->tuner_en_reg)