From patchwork Thu Mar 7 16:58:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 10843421 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 713021515 for ; Thu, 7 Mar 2019 16:59:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 586912F659 for ; Thu, 7 Mar 2019 16:59:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4CB852F65E; Thu, 7 Mar 2019 16:59:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BDA002F659 for ; Thu, 7 Mar 2019 16:59:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dLf4OgdurJLRWkKqkqGNlBo8FNV/woxnD6lSEk9tU4Q=; b=T93O/fwYWw7/40 OIqP/a95rJ+crw0Zy4scMpki2OR8h5jYQZJVOOzPwLXZJDnyiXGo/6TJjsHWEKEQ7nUnKyEbIILnf 88Hd0EtNZ8+8rlKWeS+NvgX/KuBym3iqMGqryfsceDz8fkCntRSR2uV9J3rEhI7P6F+hydZu9vQJD ObKtuB/W5908c6pS1fD89B+uPG+eOC7HlUjbSt9D9Ne0my3nBIsTQr0xPc3cR19eloVE8FOw/ngeo pNf8W/x2LNOuayNItAuHm4zrlyWAyOyIfSs3LceqmjI66cRYNfpVESRM29WR7a807oTrK+b9yEYpc Lh4FxfyDEaOmSIwnK76w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h1wN5-0002Mj-VN; Thu, 07 Mar 2019 16:59:51 +0000 Received: from mailoutvs18.siol.net ([185.57.226.209] helo=mail.siol.net) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h1wM8-00010I-L0 for linux-arm-kernel@lists.infradead.org; Thu, 07 Mar 2019 16:58:55 +0000 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Zimbra) with ESMTP id 747195237CE; Thu, 7 Mar 2019 17:58:45 +0100 (CET) X-Virus-Scanned: amavisd-new at psrvmta12.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta12.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id ll3xQKAlnVGF; Thu, 7 Mar 2019 17:58:44 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Zimbra) with ESMTPS id D13345237E2; Thu, 7 Mar 2019 17:58:44 +0100 (CET) Received: from localhost.localdomain (cpe-86-58-52-202.static.triera.net [86.58.52.202]) (Authenticated sender: 031275009) by mail.siol.net (Zimbra) with ESMTPSA id 794D15237CE; Thu, 7 Mar 2019 17:58:42 +0100 (CET) From: Jernej Skrabec To: maxime.ripard@bootlin.com, wens@csie.org Subject: [PATCH 3/6] dmaengine: sun6i: Add a quirk for setting DRQ fields Date: Thu, 7 Mar 2019 17:58:26 +0100 Message-Id: <20190307165829.9086-4-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190307165829.9086-1-jernej.skrabec@siol.net> References: <20190307165829.9086-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190307_085853_612978_E2F165DA X-CRM114-Status: GOOD ( 11.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jernej.skrabec@siol.net, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, vkoul@kernel.org, robh+dt@kernel.org, dmaengine@vger.kernel.org, dan.j.williams@intel.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP H6 DMA has more than 32 possible DRQs. That means that current maximum of 31 DRQs is not enough anymore. Add a quirk which will set source and destination DRQ number. Signed-off-by: Jernej Skrabec --- drivers/dma/sun6i-dma.c | 48 ++++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 20 deletions(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 761555080325..9dd23b76d841 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -68,15 +68,15 @@ #define DMA_CHAN_LLI_ADDR 0x08 #define DMA_CHAN_CUR_CFG 0x0c -#define DMA_CHAN_MAX_DRQ 0x1f -#define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & DMA_CHAN_MAX_DRQ) +#define DMA_CHAN_MAX_DRQ_A31 0x1f +#define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31) #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) #define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7) #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6) #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) -#define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16) +#define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16) #define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) #define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16) #define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16) @@ -125,6 +125,7 @@ struct sun6i_dma_config { */ void (*clock_autogate_enable)(struct sun6i_dma_dev *); void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst); + void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq); u32 src_burst_lengths; u32 dst_burst_lengths; u32 src_addr_widths; @@ -311,6 +312,12 @@ static void sun6i_set_burst_length_h3(u32 *p_cfg, s8 src_burst, s8 dst_burst) DMA_CHAN_CFG_DST_BURST_H3(dst_burst); } +static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq) +{ + *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_A31(src_drq) | + DMA_CHAN_CFG_DST_DRQ_A31(dst_drq); +} + static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) { struct sun6i_desc *txd = pchan->desc; @@ -634,14 +641,13 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( burst = convert_burst(8); width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES); - v_lli->cfg = DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | - DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | - DMA_CHAN_CFG_DST_LINEAR_MODE | + v_lli->cfg = DMA_CHAN_CFG_DST_LINEAR_MODE | DMA_CHAN_CFG_SRC_LINEAR_MODE | DMA_CHAN_CFG_SRC_WIDTH(width) | DMA_CHAN_CFG_DST_WIDTH(width); sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst); + sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM); sun6i_dma_lli_add(NULL, v_lli, p_lli, txd); @@ -695,9 +701,8 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( v_lli->dst = sconfig->dst_addr; v_lli->cfg = lli_cfg | DMA_CHAN_CFG_DST_IO_MODE | - DMA_CHAN_CFG_SRC_LINEAR_MODE | - DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | - DMA_CHAN_CFG_DST_DRQ(vchan->port); + DMA_CHAN_CFG_SRC_LINEAR_MODE; + sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); dev_dbg(chan2dev(chan), "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", @@ -710,9 +715,8 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( v_lli->dst = sg_dma_address(sg); v_lli->cfg = lli_cfg | DMA_CHAN_CFG_DST_LINEAR_MODE | - DMA_CHAN_CFG_SRC_IO_MODE | - DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | - DMA_CHAN_CFG_SRC_DRQ(vchan->port); + DMA_CHAN_CFG_SRC_IO_MODE; + sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); dev_dbg(chan2dev(chan), "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", @@ -780,17 +784,15 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic( v_lli->dst = sconfig->dst_addr; v_lli->cfg = lli_cfg | DMA_CHAN_CFG_DST_IO_MODE | - DMA_CHAN_CFG_SRC_LINEAR_MODE | - DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | - DMA_CHAN_CFG_DST_DRQ(vchan->port); + DMA_CHAN_CFG_SRC_LINEAR_MODE; + sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); } else { v_lli->src = sconfig->src_addr; v_lli->dst = buf_addr + period_len * i; v_lli->cfg = lli_cfg | DMA_CHAN_CFG_DST_LINEAR_MODE | - DMA_CHAN_CFG_SRC_IO_MODE | - DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | - DMA_CHAN_CFG_SRC_DRQ(vchan->port); + DMA_CHAN_CFG_SRC_IO_MODE; + sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); } prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); @@ -1055,6 +1057,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { .nr_max_requests = 30, .nr_max_vchans = 53, .set_burst_length = sun6i_set_burst_length_a31, + .set_drq = sun6i_set_drq_a31, .src_burst_lengths = BIT(1) | BIT(8), .dst_burst_lengths = BIT(1) | BIT(8), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1076,6 +1079,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { .nr_max_vchans = 37, .clock_autogate_enable = sun6i_enable_clock_autogate_a23, .set_burst_length = sun6i_set_burst_length_a31, + .set_drq = sun6i_set_drq_a31, .src_burst_lengths = BIT(1) | BIT(8), .dst_burst_lengths = BIT(1) | BIT(8), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1092,6 +1096,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { .nr_max_vchans = 39, .clock_autogate_enable = sun6i_enable_clock_autogate_a23, .set_burst_length = sun6i_set_burst_length_a31, + .set_drq = sun6i_set_drq_a31, .src_burst_lengths = BIT(1) | BIT(8), .dst_burst_lengths = BIT(1) | BIT(8), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1115,6 +1120,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { .nr_max_vchans = 34, .clock_autogate_enable = sun6i_enable_clock_autogate_h3, .set_burst_length = sun6i_set_burst_length_h3, + .set_drq = sun6i_set_drq_a31, .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1134,6 +1140,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { static struct sun6i_dma_config sun50i_a64_dma_cfg = { .clock_autogate_enable = sun6i_enable_clock_autogate_h3, .set_burst_length = sun6i_set_burst_length_h3, + .set_drq = sun6i_set_drq_a31, .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1157,6 +1164,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { .nr_max_vchans = 24, .clock_autogate_enable = sun6i_enable_clock_autogate_a23, .set_burst_length = sun6i_set_burst_length_a31, + .set_drq = sun6i_set_drq_a31, .src_burst_lengths = BIT(1) | BIT(8), .dst_burst_lengths = BIT(1) | BIT(8), .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | @@ -1272,8 +1280,8 @@ static int sun6i_dma_probe(struct platform_device *pdev) ret = of_property_read_u32(np, "dma-requests", &sdc->max_request); if (ret && !sdc->max_request) { dev_info(&pdev->dev, "Missing dma-requests, using %u.\n", - DMA_CHAN_MAX_DRQ); - sdc->max_request = DMA_CHAN_MAX_DRQ; + DMA_CHAN_MAX_DRQ_A31); + sdc->max_request = DMA_CHAN_MAX_DRQ_A31; } /*