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bh=tIxoei8cMS93Syn3k86yFQB4xBzYr/pMH0+fkkNbDnE=; b=cJBXdAYtZjGArrkn2m+9seQysEHoxaC2MKM6KGyxKqJNsK+86y7me4AAsODncpQTjE k0j5lj87S3jieK0Okka9BnPcAvBKAwGwKoN01NSfH7u43bVfw2og6GF8NTsZQBnnAZ1p K8una8wB2I/8f9jcnBTvREidbmA3GK9HijPNmFG0UQTvtjtWq+mj4wJlVIJF+Vj7xWJr Gxez1E7jeC7DNmT60vKtcY78sockV55IBUHnV4/Wn1hShdzqA81v76AFqFqIlBqXaDGO il4euH0Xpky/7Od1V+LnHxjW3ZYdZ3F80U2h6QgsKsY5j6RSBE8idqJZTjLazuRKK503 p52Q== X-Gm-Message-State: APjAAAVSQpSieQRj02fc7QRGE5n6rU19caSf230FSVP6fh+xGt1ncZ9q jiIFH+VSQoAY3AcWbj8htlw= X-Google-Smtp-Source: APXvYqwubchsafWIDQB02vemw1/aYyPDWwnObP9MrV3uusjCM+OevhhRHvqvZwsDh2WXrYZX/YNdow== X-Received: by 2002:ac8:80e:: with SMTP id u14mr7312942qth.123.1552155616018; Sat, 09 Mar 2019 10:20:16 -0800 (PST) Received: from localhost.localdomain ([2601:153:900:ebb:f162:44b2:3d44:afcd]) by smtp.gmail.com with ESMTPSA id j4sm367526qta.76.2019.03.09.10.20.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Mar 2019 10:20:15 -0800 (PST) From: Peter Geis To: Rob Herring Subject: [PATCH] arm64: dts: rockchip: Fix rk3328 rgmii high tx error rate Date: Sat, 9 Mar 2019 18:20:13 +0000 Message-Id: <20190309182013.22162-1-pgwipeout@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190309_102018_513176_C610FB46 X-CRM114-Status: GOOD ( 12.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , linux-rockchip@lists.infradead.org, Peter Geis , Heiko Stuebner , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Several rk3328 based boards experience high rgmii tx error rates. This is due to several pins in the rk3328.dtsi rgmii pinmux that are missing a pull level setting. This causes the pinmux driver to default to 0ma. Fix this by setting those pins to 12ma, consistent with the other tx pins. This allows much higher data rates with much fewer retries and no recorded tx errors. Tested on the rk3328-roc-cc board. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 84f14b132e8f..48a4477ebe58 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -1673,19 +1673,19 @@ <1 RK_PC1 2 &pcfg_pull_none_12ma>, /* mac_txclk */ - <0 RK_PB0 1 &pcfg_pull_none>, + <0 RK_PB0 1 &pcfg_pull_none_12ma>, /* mac_txen */ - <0 RK_PB4 1 &pcfg_pull_none>, + <0 RK_PB4 1 &pcfg_pull_none_12ma>, /* mac_clk */ - <0 RK_PD0 1 &pcfg_pull_none>, + <0 RK_PD0 1 &pcfg_pull_none_12ma>, /* mac_txd1 */ - <0 RK_PC0 1 &pcfg_pull_none>, + <0 RK_PC0 1 &pcfg_pull_none_12ma>, /* mac_txd0 */ - <0 RK_PC1 1 &pcfg_pull_none>, + <0 RK_PC1 1 &pcfg_pull_none_12ma>, /* mac_txd3 */ - <0 RK_PC7 1 &pcfg_pull_none>, + <0 RK_PC7 1 &pcfg_pull_none_12ma>, /* mac_txd2 */ - <0 RK_PC6 1 &pcfg_pull_none>; + <0 RK_PC6 1 &pcfg_pull_none_12ma>; }; rmiim1_pins: rmiim1-pins {