diff mbox series

[2/3] arm64: dts: ls1028a: Corrected the SATA ecc address.

Message ID 20190311072014.36565-2-peng.ma@nxp.com (mailing list archive)
State New, archived
Headers show
Series [1/3] dt-bindings: ahci-fsl-qoriq: add ls1028a chip name to the list | expand

Commit Message

Peng Ma March 11, 2019, 7:20 a.m. UTC
Ls1028a SATA ecc address with more than 32 bit, so we should corrrect the
address.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

Comments

Shawn Guo April 11, 2019, 1:35 a.m. UTC | #1
On Mon, Mar 11, 2019 at 03:20:13PM +0800, Peng Ma wrote:
> Ls1028a SATA ecc address with more than 32 bit, so we should corrrect the
> address.
> 
> Signed-off-by: Peng Ma <peng.ma@nxp.com>

Applied, thanks.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index a8cf92a..3fcbd0a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -277,7 +277,7 @@ 
 		sata: sata@3200000 {
 			compatible = "fsl,ls1028a-ahci";
 			reg = <0x0 0x3200000 0x0 0x10000>,
-				<0x0 0x20140520 0x0 0x4>;
+				<0x7 0x100520 0x0 0x4>;
 			reg-names = "ahci", "sata-ecc";
 			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clockgen 4 1>;