From patchwork Thu Mar 28 10:37:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Murray X-Patchwork-Id: 10874781 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C03BD13B5 for ; Thu, 28 Mar 2019 10:39:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A6866205AD for ; Thu, 28 Mar 2019 10:39:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9A739284E4; Thu, 28 Mar 2019 10:39:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 198FD205AD for ; Thu, 28 Mar 2019 10:39:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DhJO0LyqIbEHSB7/XwsA6RLTkC3X6RP5cD3CJ32jog0=; b=eXjaclb/vBCQVs VvK90IXF4G7dblZ4MLk/Sl4RgIs1LOqV0FUbLaoRMQr5sPSTUhf6OE9lIK1J88p1T062bNjGpfTeV /k1v8HZkjLnR+NTNQKnpvnG4rnCsmqjRNwBBG255z89r6hbd76dsymGEHpppJHbefQJSYJFZBKuDh 42ULCglvD1ekv9kt6HGW8atYBuUvLjg6SLHlU4isKcuIrcMKdUfVaA03bIQ6uQA9uMkAjBWyB6Nhn TPrm2v8lrbvuTUdtb6pFBV/HY4j/uZOD4MWkHc845bFkzT2BnYZPwmFk7q5NAX8f67B/ZvcdsaD/I cm4wNlduy7Andna2pqbQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h9SRY-0008VF-15; Thu, 28 Mar 2019 10:39:32 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h9SPz-0006mf-Uh for linux-arm-kernel@lists.infradead.org; Thu, 28 Mar 2019 10:38:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9D12A165C; Thu, 28 Mar 2019 03:37:55 -0700 (PDT) Received: from e119886-lin.cambridge.arm.com (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B046A3F59C; Thu, 28 Mar 2019 03:37:53 -0700 (PDT) From: Andrew Murray To: Christoffer Dall , Marc Zyngier , Catalin Marinas , Will Deacon , Mark Rutland Subject: [PATCH v12 8/8] arm64: docs: document perf event attributes Date: Thu, 28 Mar 2019 10:37:31 +0000 Message-Id: <20190328103731.27264-9-andrew.murray@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190328103731.27264-1-andrew.murray@arm.com> References: <20190328103731.27264-1-andrew.murray@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190328_033756_282827_69C0711E X-CRM114-Status: GOOD ( 14.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Julien Thierry , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, Suzuki K Poulose Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The interaction between the exclude_{host,guest} flags, exclude_{user,kernel,hv} flags and presence of VHE can result in different exception levels being filtered by the ARMv8 PMU. As this can be confusing let's document how they work on arm64. Signed-off-by: Andrew Murray --- Documentation/arm64/perf.txt | 74 ++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/arm64/perf.txt diff --git a/Documentation/arm64/perf.txt b/Documentation/arm64/perf.txt new file mode 100644 index 000000000000..604446c1f720 --- /dev/null +++ b/Documentation/arm64/perf.txt @@ -0,0 +1,74 @@ +Perf Event Attributes +===================== + +Author: Andrew Murray +Date: 2019-03-06 + +exclude_user +------------ + +This attribute excludes userspace. + +Userspace always runs at EL0 and thus this attribute will exclude EL0. + + +exclude_kernel +-------------- + +This attribute excludes the kernel. + +The kernel runs at EL2 with VHE and EL1 without. Guest kernels always run +at EL1. + +This attribute will exclude EL1 and additionally EL2 on a VHE system. + + +exclude_hv +---------- + +This attribute excludes the hypervisor, we ignore this flag on a VHE system +as we consider the host kernel to be the hypervisor. + +On a non-VHE system we consider the hypervisor to be any code that runs at +EL2 which is predominantly used for guest/host transitions. + +This attribute will exclude EL2 on a non-VHE system. + + +exclude_host / exclude_guest +---------------------------- + +This attribute excludes the KVM host. + +The KVM host may run at EL0 (userspace), EL1 (non-VHE kernel) and EL2 (VHE +kernel or non-VHE hypervisor). + +The KVM guest may run at EL0 (userspace) and EL1 (kernel). + +Due to the overlapping exception levels between host and guests we cannot +exclusively rely on the PMU's hardware exception filtering - therefore we +must enable/disable counting on the entry and exit to the guest. This is +performed differently on VHE and non-VHE systems. + +For non-VHE systems we exclude EL2 for exclude_host - upon entering and +exiting the guest we disable/enable the event as appropriate based on the +exclude_host and exclude_guest attributes. + +For VHE systems we exclude EL1 for exclude_guest and exclude both EL0,EL2 +for exclude_host. Upon entering and exiting the guest we modify the event +to include/exclude EL0 as appropriate based on the exclude_host and +exclude_guest attributes. + + +Accuracy +-------- + +On non-VHE systems we enable/disable counters on the entry/exit of +host/guest transition at EL2 - however there is a period of time between +enabling/disabling the counters and entering/exiting the guest. We are +able to eliminate counters counting host events on the boundaries of guest +entry/exit when counting guest events by filtering out EL2 for +exclude_host. However when using !exclude_hv there is a small blackout +window at the guest entry/exit where host events are not captured. + +On VHE systems there are no blackout windows.