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Sat, 30 Mar 2019 17:07:44 +0000 From: Daniel Baluta To: "shawnguo@kernel.org" Subject: [PATCH] arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes Thread-Topic: [PATCH] arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes Thread-Index: AQHU5xsXTkClBElNYkSLBv/JPYYQCg== Date: Sat, 30 Mar 2019 17:07:44 +0000 Message-ID: <20190330170725.24360-1-daniel.baluta@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR0102CA0060.eurprd01.prod.exchangelabs.com (2603:10a6:803::37) To VI1PR0402MB3357.eurprd04.prod.outlook.com (2603:10a6:803:2::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=daniel.baluta@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [212.146.100.6] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6487ce5b-14b6-4f16-38f3-08d6b5323992 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4618075)(2017052603328)(7153060)(7193020); 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Wang" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP lpuart nodes are part of the ADMA subsystem. See Audio DMA memory map in iMX8 QXP RM [1] This patch is based on the dtsi file initially submitted by Teo Hall in i.MX NXP internal tree. [1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf Signed-off-by: Teo Hall Signed-off-by: Daniel Baluta Reviewed-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 0cb939861a60..1adfe15c2ea5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -193,6 +193,39 @@ status = "disabled"; }; + adma_lpuart1: serial@5a070000 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x5a070000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_UART_1>; + status = "disabled"; + }; + + adma_lpuart2: serial@5a080000 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x5a080000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_UART_2>; + status = "disabled"; + } + + adma_lpuart3: serial@5a090000 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + reg = <0x5a090000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_UART_3>; + status = "disabled"; + } + adma_i2c0: i2c@5a800000 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x5a800000 0x4000>;