diff mbox series

[2/2] ARM: OMAP2+: sleep43xx: Run EMIF HW leveling on resume path

Message ID 20190402165743.28106-3-d-gerlach@ti.com (mailing list archive)
State Mainlined, archived
Commit 11140cc40ddc3e7a2f2e3352e8a0587a93ba75df
Headers show
Series ARM: OMAP2+: AM43x: Support DDR HW leveling suspend/resume | expand

Commit Message

Dave Gerlach April 2, 2019, 4:57 p.m. UTC 
When returning from DeepSleep mode on AM437x platforms the EMIF must run
DDR hardware leveling, same as done during u-boot, to properly restore the
EMIF PHY to it's operational state on platforms using DDR3.

Call the ti-emif-sram-pm run_hw_leveling routine to perform this. This
happens after all other EMIF values are restored so the exact same
configuration used at boot is used at the end of EMIF resume as well.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 arch/arm/mach-omap2/sleep43xx.S | 3 +++
 1 file changed, 3 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S
index 5b9343b58fc7..0c1031442571 100644
--- a/arch/arm/mach-omap2/sleep43xx.S
+++ b/arch/arm/mach-omap2/sleep43xx.S
@@ -368,6 +368,9 @@  wait_emif_enable1:
 	mov     r1, #AM43XX_EMIF_POWEROFF_DISABLE
 	str     r1, [r2, #0x0]
 
+	ldr     r1, [r9, #EMIF_PM_RUN_HW_LEVELING]
+	blx     r1
+
 #ifdef CONFIG_CACHE_L2X0
 	ldr	r2, l2_cache_base
 	ldr	r0, [r2, #L2X0_CTRL]