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bh=SAt54gusO22M7wlCjXKs+Y6DbEbN3JCXkJVbAiVcyrQ=; b=FhFEQJGU8N1HJUf9NpnInwDL+9id/+0wF0yUkuuBQmQWobahKDJPBajULXqsH6I9wS X7lIsvUtxkt0dBV+eN8hC+Kgh3mSTUmRJ3MNXO7e/8PgSH5vFksnoNgSzSJEdWusPS75 zrKhnNNSEh2msCC8/7B3MU3GS+lT1pVhq9dPQdg8NI5kiFuhmi5bBNEb7qJZFfQ4uVxP gcR20ZAPs0LM7PyZVZvSFQYVcDYCsHhXrn2Eu6uJr0NbtmxBywya9NgBeNq/j0duzMyG 7HW2+tidbrBuZ4i5vYuOlNPgK1Ev4USGcYipWV6cvArPHQdt0bFcmeRgGO8ry9mH+Hwy Hf0A== X-Gm-Message-State: APjAAAVpim6Uc9hWXf1FUHTg00kNLq+ahTOQzycyW6joObLDcjfBbdiX 0bvvbwfTuP+BrXPgv6iol1IN9WPiwPQ= X-Google-Smtp-Source: APXvYqyqLPVOgsJdntpitDgkDe8xtxV8hGaTgnlPVyq9j2/fptKaLJIl4ucuD98Wnki638HBqz6BjA== X-Received: by 2002:a62:ab14:: with SMTP id p20mr3336646pff.23.1554349000298; Wed, 03 Apr 2019 20:36:40 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:36:39 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 14/20] coresight: tmc-etr: Introduce the notion of process ID to ETR devices Date: Wed, 3 Apr 2019 21:35:35 -0600 Message-Id: <20190404033541.14072-15-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190403_233642_897479_9B155222 X-CRM114-Status: GOOD ( 15.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, alexander.shishkin@linux.intel.com, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, peterz@infradead.org, mike.leach@arm.com, leo.yan@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In preparation to support CPU-wide trace scenarios, introduce the notion of process ID to ETR devices. That way events monitoring the same process can use the same etr_buf, allowing multiple CPUs to use the same sink. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index ac1efdfc0d07..e1774d4bb5f3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include "coresight-catu.h" #include "coresight-etm-perf.h" @@ -25,6 +26,7 @@ struct etr_flat_buf { /* * etr_perf_buffer - Perf buffer used for ETR * @etr_buf - Actual buffer used by the ETR + * @pid - The PID this etr_perf_buffer belongs to. * @snaphost - Perf session mode * @head - handle->head at the beginning of the session. * @nr_pages - Number of pages in the ring buffer. @@ -32,6 +34,7 @@ struct etr_flat_buf { */ struct etr_perf_buffer { struct etr_buf *etr_buf; + pid_t pid; bool snapshot; unsigned long head; int nr_pages; @@ -1276,6 +1279,7 @@ static void *tmc_alloc_etr_buffer(struct coresight_device *csdev, return NULL; } + etr_perf->pid = task_pid_nr(event->owner); etr_perf->snapshot = snapshot; etr_perf->nr_pages = nr_pages; etr_perf->pages = pages;