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bh=H9+OTr1OpfrOYtthYPTeqD/UZckEAYj6DoPWjl6ycEY=; b=fdKmzozk91Aa8tyjyr6s8NJPXSvJblWerFjWtLHjE89bHiwnK2Mp1X542/c+P3AMj6 D8D7ffsnhJtpeIU07pfZWlS+EEdiKph+eogWStLcajVrGKvmDilEjuGM9pGoD0WXj3At rEcgt+ezqgCyyIwpWoUMb9oky8AtZmuEFCh+0Yh4HKisvIuzvVjyMHtBpEJokgdElP94 +gqTclLC/tMI4PwDljWnHCJBIxudKKC1tsB7PBq5YWXh1eThyUdy/KPma7YrxzKG2gNP sFUJ5qg5PH6Iju2FVqUgkcfYnyAysxV3LldR5sBkE5r+bvCeoQezk7gHl54rrikpUoQt 47UA== X-Gm-Message-State: APjAAAUid6zdw9HadSwVW+CTyRKQd43w+06zBtxCzbWYOfT0BiiTzL6o 9d9Z5Eg6f5CI9sV417dB7OdSam1UZRk= X-Google-Smtp-Source: APXvYqw3tJWWYHJETjByD6pMXcwDX2pb9RX8aFl/XUsX9IvhUHKsvCTjv8Wh/Gx8hl45MnhwXmIS4Q== X-Received: by 2002:a17:902:3283:: with SMTP id z3mr3762736plb.236.1554349003815; Wed, 03 Apr 2019 20:36:43 -0700 (PDT) Received: from xps15.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id u5sm12212780pfm.121.2019.04.03.20.36.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 03 Apr 2019 20:36:43 -0700 (PDT) From: Mathieu Poirier To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 15/20] coresight: tmc-etr: Introduce the notion of reference counting to ETR devices Date: Wed, 3 Apr 2019 21:35:36 -0600 Message-Id: <20190404033541.14072-16-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org> References: <20190404033541.14072-1-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190404_043645_516114_A261C2B3 X-CRM114-Status: GOOD ( 14.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, alexander.shishkin@linux.intel.com, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, peterz@infradead.org, mike.leach@arm.com, leo.yan@linaro.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds reference counting to struct etr_buf so that, in CPU-wide trace scenarios, shared buffers can be disposed of when no longer used. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 5 +++++ drivers/hwtracing/coresight/coresight-tmc.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index e1774d4bb5f3..1346474ac019 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -1221,7 +1222,11 @@ get_perf_etr_buf_per_thread(struct tmc_drvdata *drvdata, * with memory allocation. */ etr_buf = alloc_etr_buf(drvdata, event, nr_pages, pages, snapshot); + if (IS_ERR(etr_buf)) + goto out; + refcount_set(&etr_buf->refcount, 1); +out: return etr_buf; } diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 487c53701e9c..ee44906dffe8 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -9,6 +9,7 @@ #include #include +#include #define TMC_RSZ 0x004 #define TMC_STS 0x00c @@ -133,6 +134,7 @@ struct etr_buf_operations; /** * struct etr_buf - Details of the buffer used by ETR + * refcount ; Number of sources currently using this etr_buf. * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc. * @full : Trace data overflow * @size : Size of the buffer. @@ -143,6 +145,7 @@ struct etr_buf_operations; * @private : Backend specific information for the buf */ struct etr_buf { + refcount_t refcount; enum etr_mode mode; bool full; ssize_t size;