diff --git a/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
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+++ b/Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
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+Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
+===================================
+
+For some SoCs, the CPU frequency subset and voltage value of each OPP
+varies based on the silicon variant in use. Allwinner Process Voltage
+Scaling Tables defines the voltage and frequency value  based on the
+speedbin blown in the efuse combination. The sunxi-cpufreq-nvmem driver
+reads the efuse value from the SoC to provide the OPP framework with
+required information.
+
+Required properties:
+--------------------
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+	- 'operating-points-v2-sunxi-cpu'.
+- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
+		efuse registers that has information about the
+		speedbin that is used to select the right frequency/voltage
+		value pair.
+		Please refer the for nvmem-cells
+		bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
+		and also examples below.
+
+In every OPP node:
+- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
+		    Bitmap:
+			0:	speedbin 0
+			1:	speedbin 1
+			2:	speedbin 2
+			3-31:	unused
+
+Example 1:
+---------
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <0>;
+			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <1>;
+			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <2>;
+			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53";
+			device_type = "cpu";
+			reg = <3>;
+			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+		};
+        };
+
+	cpu_opp_table: opp_table {
+		compatible = "operating-points-v2-sunxi-cpu";
+		nvmem-cells = <&speedbin_efuse>;
+		opp-shared;
+
+		opp-480000000-0 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <880000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-720000000-0 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-microvolt = <880000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-816000000-0 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <880000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-888000000-0 {
+			opp-hz = /bits/ 64 <888000000>;
+			opp-microvolt = <940000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1080000000-0 {
+			opp-hz = /bits/ 64 <1080000000>;
+			opp-microvolt = <1060000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1320000000-0 {
+			opp-hz = /bits/ 64 <1320000000>;
+			opp-microvolt = <1160000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1488000000-0 {
+			opp-hz = /bits/ 64 <1488000000>;
+			opp-microvolt = <1160000>;
+			opp-supported-hw = <0x1>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp-480000000-1 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <820000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-720000000-1 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-microvolt = <820000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-816000000-1 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <820000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-888000000-1 {
+			opp-hz = /bits/ 64 <888000000>;
+			opp-microvolt = <820000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1080000000-1 {
+			opp-hz = /bits/ 64 <1080000000>;
+			opp-microvolt = <880000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1320000000-1 {
+			opp-hz = /bits/ 64 <1320000000>;
+			opp-microvolt = <940000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1488000000-1 {
+			opp-hz = /bits/ 64 <1488000000>;
+			opp-microvolt = <1000000>;
+			opp-supported-hw = <0x2>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp-480000000-2 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <800000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-720000000-2 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-microvolt = <800000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-816000000-2 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <800000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-888000000-2 {
+			opp-hz = /bits/ 64 <888000000>;
+			opp-microvolt = <800000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1080000000-2 {
+			opp-hz = /bits/ 64 <1080000000>;
+			opp-microvolt = <840000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1320000000-2 {
+			opp-hz = /bits/ 64 <1320000000>;
+			opp-microvolt = <900000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+		opp-1488000000-2 {
+			opp-hz = /bits/ 64 <1488000000>;
+			opp-microvolt = <960000>;
+			opp-supported-hw = <0x4>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+	};
+
+....
+soc {
+....
+	sid: sid@3006000 {
+		compatible = "allwinner,sun50i-h6-sid";
+		reg = <0x03006000 0x400>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		....
+		speedbin_efuse: speed@1c {
+			reg = <0x1c 4>;
+		};
+        };
+};
