From patchwork Tue Apr 16 19:27:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 10903961 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 63476922 for ; Tue, 16 Apr 2019 19:28:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4265C286E5 for ; Tue, 16 Apr 2019 19:28:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3600228A08; Tue, 16 Apr 2019 19:28:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DA8BF286E5 for ; Tue, 16 Apr 2019 19:28:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vT9/LTpl8EtKFAt6OFM9GfLMXPG19vASh9c0LXGn4kw=; b=iz6eekcP5VXHER uja5GvjjFEYkufRZeGi/5ZbpkDMbbxbQIHlQ7BmOjdyn/JWla8Vs/FJezst1cfiFH2fe2Ziw9oBs4 iLmI1fquOJfnGFkc7gvbIqdk9p0fuzQ1RiQGZCxujCDF5RE6s8vF8ayzu5YU1sOF7IYOcASr1GMgE qN/T/BoVdBgWHGVbJTqrr3ztThd5Im2B6bga65HVsJOO1HpzTjKR2fOngcsYF0+G4Nz0bmGDIRFEZ rFdJJTCGpRVjIdFQRaoqAlslD/SHU0G8tBEBcKtVbMJUDeaQwCvwtBJFxwkmbKiZja+A7DASXC3PM Py1OLQa68xojpcTe3bXg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hGTl2-00048K-Qb; Tue, 16 Apr 2019 19:28:40 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hGTkY-0003di-QL for linux-arm-kernel@lists.infradead.org; Tue, 16 Apr 2019 19:28:18 +0000 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 16 Apr 2019 12:28:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 16 Apr 2019 12:28:10 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 16 Apr 2019 12:28:10 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 16 Apr 2019 19:28:09 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 16 Apr 2019 19:28:09 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 16 Apr 2019 12:28:09 -0700 From: Vidya Sagar To: , , , , , , , , , , Subject: [PATCH V3 04/16] PCI: dwc: Perform dbi regs write lock towards the end Date: Wed, 17 Apr 2019 00:57:18 +0530 Message-ID: <20190416192730.15681-5-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190416192730.15681-1-vidyas@nvidia.com> References: <20190416192730.15681-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555442895; bh=d2fraG+ooOhN52P8jEntvECSgoDTCGy+5RiecCjDr60=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=qWzzIBLSXChGgUpnOvcx/QUWgZpzZFCZnpPPqfxuQkmAUIZ4hAWBGju4NWCmpx//W DeqHAd/pzgHfAybLf6yO8nY140gYhd7s7yqdEGOlVfQpqzPDGLFujGVCneJrG8ABZH n/8zcIiDfS0w5oyyf1f93P2/JVhR5ck0O3BK9PdAGTSQowmdUsYnkTcSsTjg8nOW/d Jzsi5MUblEpQ3PpVpdsddKT6TdYlszE7/ApPhBp9oU2gAm7h3rA0UPPZVeNEmWJTMS 9zdrIxt0xXOBpoI97tpDW10m+3JhpPprBK3UhQsmNrCbYq8OCDtm1cYChA+HDV83Hw AEyLEYvzqKtBQ== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190416_122811_195955_B3DDA914 X-CRM114-Status: UNSURE ( 6.69 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com, kthota@nvidia.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, linux-tegra@vger.kernel.org, vidyas@nvidia.com, linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Remove multiple write enable and disable sequences of dbi registers as Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by DBI write-lock enable bit thereby not allowing any further writes to BAR-0 register in config space to take place. Hence disabling write permission only towards the end. Signed-off-by: Vidya Sagar --- Changes since [v2]: * None Changes since [v1]: * None drivers/pci/controller/dwc/pcie-designware-host.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 2a5332e5ccfa..c0334c92c1a6 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -683,7 +683,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val &= 0xffff00ff; val |= 0x00000100; dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val); - dw_pcie_dbi_ro_wr_dis(pci); /* Setup bus numbers */ val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS); @@ -723,8 +722,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); - /* Enable write permission for the DBI read-only register */ - dw_pcie_dbi_ro_wr_en(pci); /* Program correct class for RC */ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); /* Better disable write permission right after the update */