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[90.86.218.216]) by smtp.gmail.com with ESMTPSA id u17sm5582862wmu.36.2019.04.17.07.47.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Apr 2019 07:47:16 -0700 (PDT) From: Bartosz Golaszewski To: Sekhar Nori , Kevin Hilman , Daniel Lezcano , Thomas Gleixner , David Lechner Subject: [RFC 2/2] clocksource: timer-davinci: add support for clocksource Date: Wed, 17 Apr 2019 16:47:09 +0200 Message-Id: <20190417144709.19588-3-brgl@bgdev.pl> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190417144709.19588-1-brgl@bgdev.pl> References: <20190417144709.19588-1-brgl@bgdev.pl> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190417_074718_638695_80686E7D X-CRM114-Status: GOOD ( 14.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Bartosz Golaszewski Extend the davinci-timer driver to also register a clock source. Signed-off-by: Bartosz Golaszewski --- drivers/clocksource/timer-davinci.c | 70 +++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/drivers/clocksource/timer-davinci.c b/drivers/clocksource/timer-davinci.c index d30f81a4088e..d630fca98123 100644 --- a/drivers/clocksource/timer-davinci.c +++ b/drivers/clocksource/timer-davinci.c @@ -42,6 +42,8 @@ #define DAVINCI_TIMER_MIN_DELTA 0x01 #define DAVINCI_TIMER_MAX_DELTA 0xfffffffe +#define DAVINCI_TIMER_CLKSRC_BITS 32 + #define DAVINCI_TIMER_TGCR_DEFAULT \ (DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED | DAVINCI_TIMER_UNRESET) @@ -59,6 +61,16 @@ struct davinci_clockevent { unsigned int enamode_mask; }; +/* + * This must be globally accessible by davinci_timer_read_sched_clock(), so + * let's keep it here. + */ +static struct { + struct clocksource dev; + void __iomem *base; + unsigned int tim_off; +} davinci_clocksource; + static struct davinci_clockevent * to_davinci_clockevent(struct clock_event_device *clockevent) { @@ -148,6 +160,32 @@ static irqreturn_t davinci_timer_irq_timer(int irq, void *data) return IRQ_HANDLED; } +static u64 notrace davinci_timer_read_sched_clock(void) +{ + return readl_relaxed(davinci_clocksource.base + + davinci_clocksource.tim_off); +} + +static u64 davinci_clocksource_read(struct clocksource *dev) +{ + return davinci_timer_read_sched_clock(); +} + +static void davinci_clocksource_init(void __iomem *base, unsigned int tim_off, + unsigned int prd_off, unsigned int shift) +{ + davinci_reg_update(base, DAVINCI_TIMER_REG_TCR, + DAVINCI_TIMER_ENAMODE_MASK << shift, + DAVINCI_TIMER_ENAMODE_DISABLED << shift); + + writel_relaxed(0x0, base + tim_off); + writel_relaxed(UINT_MAX, base + prd_off); + + davinci_reg_update(base, DAVINCI_TIMER_REG_TCR, + DAVINCI_TIMER_ENAMODE_MASK << shift, + DAVINCI_TIMER_ENAMODE_PERIODIC << shift); +} + static void davinci_timer_init(void __iomem *base) { /* Set clock to internal mode and disable it. */ @@ -235,6 +273,38 @@ int __init davinci_timer_register(struct clk *clk, DAVINCI_TIMER_MIN_DELTA, DAVINCI_TIMER_MAX_DELTA); + davinci_clocksource.dev.rating = 300; + davinci_clocksource.dev.read = davinci_clocksource_read; + davinci_clocksource.dev.mask = + CLOCKSOURCE_MASK(DAVINCI_TIMER_CLKSRC_BITS); + davinci_clocksource.dev.flags = CLOCK_SOURCE_IS_CONTINUOUS; + davinci_clocksource.base = base; + + if (timer_cfg->cmp_off) { + davinci_clocksource.dev.name = "tim12"; + davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM12; + davinci_clocksource_init(base, + DAVINCI_TIMER_REG_TIM12, + DAVINCI_TIMER_REG_PRD12, + DAVINCI_TIMER_ENAMODE_SHIFT_TIM12); + } else { + davinci_clocksource.dev.name = "tim34"; + davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM34; + davinci_clocksource_init(base, + DAVINCI_TIMER_REG_TIM34, + DAVINCI_TIMER_REG_PRD34, + DAVINCI_TIMER_ENAMODE_SHIFT_TIM34); + } + + rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate); + if (rv) { + pr_err("Unable to register clocksource"); + return rv; + } + + sched_clock_register(davinci_timer_read_sched_clock, + DAVINCI_TIMER_CLKSRC_BITS, tick_rate); + return 0; }