| Message ID | 20190419100327.31483-4-pure.logic@nexus-software.ie (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add i.MX8MM support | expand |
On 19.04.2019 13:03, Bryan O'Donoghue wrote: > This patch adds support to burn the fuses on the i.MX8MM. > > +#if defined(CONFIG_ARCH_MXC) > +#define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF > +#else > #define IMX_OCOTP_BM_CTRL_ADDR 0x0000007F > +#endif /* ARCH_MXC */ You're on an older tree; in upstream ARCH_MXC is defined on all imx6/7/8 so can't be used to distinguish. Maybe move to ocotp_params instead? The number of valid ADDR bits in OCOTP_CTRL also seems to vary between some imx6 variants. As far as I can tell high ADDR bits are RSVD0 based on total number of fuses in the chip. Reading that zero from hardware and writing it back should be harmless. Maybe enlarge to 0xFF, maximum of all current parts? > +static const struct ocotp_params imx8mm_params = { > + .nregs = 64, Why nregs=64? fusemap in RM documents fuses from 0x400 and 0x13f0 so 256 in total. But most of those are reserved anyway. -- Regards, Leonard
On 19/04/2019 11:32, Leonard Crestez wrote: > On 19.04.2019 13:03, Bryan O'Donoghue wrote: >> This patch adds support to burn the fuses on the i.MX8MM. >> >> +#if defined(CONFIG_ARCH_MXC) >> +#define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF >> +#else >> #define IMX_OCOTP_BM_CTRL_ADDR 0x0000007F >> +#endif /* ARCH_MXC */ > > You're on an older tree; in upstream ARCH_MXC is defined on all imx6/7/8 > so can't be used to distinguish. Maybe move to ocotp_params instead? > The number of valid ADDR bits in OCOTP_CTRL also seems to vary between > some imx6 variants. > > As far as I can tell high ADDR bits are RSVD0 based on total number of > fuses in the chip. Reading that zero from hardware and writing it back > should be harmless. > > Maybe enlarge to 0xFF, maximum of all current parts? putative yes.. > >> +static const struct ocotp_params imx8mm_params = { >> + .nregs = 64, > > Why nregs=64? fusemap in RM documents fuses from 0x400 and 0x13f0 so 256 > in total. But most of those are reserved anyway. Hrmm. I did print out all of the address offsets all the way up to what is documented @ 3035_07B0h but, now that you ask the question I will check that again. I'll rebase this against linux-next/master. --- bod
On 19/04/2019 12:48, Bryan O'Donoghue wrote: > On 19/04/2019 11:32, Leonard Crestez wrote: >> On 19.04.2019 13:03, Bryan O'Donoghue wrote: >>> This patch adds support to burn the fuses on the i.MX8MM. >>> +static const struct ocotp_params imx8mm_params = { >>> + .nregs = 64, >> >> Why nregs=64? fusemap in RM documents fuses from 0x400 and 0x13f0 so 256 >> in total. But most of those are reserved anyway. That should be 60, not 64 the address range for i.M8XMM is from 0x400 - 0x7b0 unlike i.MX7S/D 0x400 - 0x7F0. i.MX 8M Mini Applications Processor Reference Manual, Rev. 1, 03/2019 page 834 True enough the 8MQ has 256 regs but, 8mm is much smaller. --- bod
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index 08a9b1ef8ae4..b6e71c34a393 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -45,7 +45,12 @@ #define IMX_OCOTP_ADDR_DATA2 0x0040 #define IMX_OCOTP_ADDR_DATA3 0x0050 +#if defined(CONFIG_ARCH_MXC) +#define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF +#else #define IMX_OCOTP_BM_CTRL_ADDR 0x0000007F +#endif /* ARCH_MXC */ + #define IMX_OCOTP_BM_CTRL_BUSY 0x00000100 #define IMX_OCOTP_BM_CTRL_ERROR 0x00000200 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400 @@ -444,6 +449,12 @@ static const struct ocotp_params imx7ulp_params = { .bank_address_words = 0, }; +static const struct ocotp_params imx8mm_params = { + .nregs = 64, + .bank_address_words = 0, + .set_timing = imx_ocotp_set_imx6_timing, +}; + static const struct of_device_id imx_ocotp_dt_ids[] = { { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params }, { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params }, @@ -453,6 +464,7 @@ static const struct of_device_id imx_ocotp_dt_ids[] = { { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params }, { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params }, { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params }, + { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params }, { }, }; MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
This patch adds support to burn the fuses on the i.MX8MM. https://www.nxp.com/webapp/Download?colCode=IMX8MMRM The i.MX8MM is similar to i.MX6 processors in terms of addressing and clock setup. Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> --- drivers/nvmem/imx-ocotp.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)