| Message ID | 20190424052004.6270-6-vidyas@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Tegra194 PCIe support | expand |
On Wed, Apr 24, 2019 at 6:19:53, Vidya Sagar <vidyas@nvidia.com> wrote: > Move PCIe config space capability search API to common DesignWare file > as this can be used by both host and ep mode codes. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> > --- > Changes from [v4]: > * Removed redundant APIs in pcie-designware-ep.c file after moving them > to pcie-designware.c file based on Bjorn's comments. > > Changes from [v3]: > * Rebased to linux-next top of the tree > > Changes from [v2]: > * None > > Changes from [v1]: > * Removed dw_pcie_find_next_ext_capability() API from here and made a > separate patch for that > > .../pci/controller/dwc/pcie-designware-ep.c | 37 +----------------- > drivers/pci/controller/dwc/pcie-designware.c | 39 +++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 2 + > 3 files changed, 43 insertions(+), 35 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index 2bf5a35c0570..65f479250087 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -40,39 +40,6 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) > __dw_pcie_ep_reset_bar(pci, bar, 0); > } > > -static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, > - u8 cap) > -{ > - u8 cap_id, next_cap_ptr; > - u16 reg; > - > - if (!cap_ptr) > - return 0; > - > - reg = dw_pcie_readw_dbi(pci, cap_ptr); > - cap_id = (reg & 0x00ff); > - > - if (cap_id > PCI_CAP_ID_MAX) > - return 0; > - > - if (cap_id == cap) > - return cap_ptr; > - > - next_cap_ptr = (reg & 0xff00) >> 8; > - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); > -} > - > -static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) > -{ > - u8 next_cap_ptr; > - u16 reg; > - > - reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); > - next_cap_ptr = (reg & 0x00ff); > - > - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); > -} > - > static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, > struct pci_epf_header *hdr) > { > @@ -612,9 +579,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); > return -ENOMEM; > } > - ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI); > + ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); > > - ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); > + ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX); > > offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); > if (offset) { > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 8e0081ccf83b..ed21e861df82 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -20,6 +20,45 @@ > #define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4) > #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29) > > +/* > + * These APIs are different from standard pci_find_*capability() APIs in the > + * sense that former can only be used post device enumeration as they require > + * 'struct pci_dev *' pointer whereas these APIs require 'struct dw_pcie *' > + * pointer and can be used before link up also. > + */ > +static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, > + u8 cap) > +{ > + u8 cap_id, next_cap_ptr; > + u16 reg; > + > + if (!cap_ptr) > + return 0; > + > + reg = dw_pcie_readw_dbi(pci, cap_ptr); > + cap_id = (reg & 0x00ff); > + > + if (cap_id > PCI_CAP_ID_MAX) > + return 0; > + > + if (cap_id == cap) > + return cap_ptr; > + > + next_cap_ptr = (reg & 0xff00) >> 8; > + return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); > +} > + > +u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) > +{ > + u8 next_cap_ptr; > + u16 reg; > + > + reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); > + next_cap_ptr = (reg & 0x00ff); > + > + return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); > +} > + > int dw_pcie_read(void __iomem *addr, int size, u32 *val) > { > if (!IS_ALIGNED((uintptr_t)addr, size)) { > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index 9ee98ced1ef6..35160b4ce929 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -248,6 +248,8 @@ struct dw_pcie { > #define to_dw_pcie_from_ep(endpoint) \ > container_of((endpoint), struct dw_pcie, ep) > > +u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); > + Can you remove this extra line space? > int dw_pcie_read(void __iomem *addr, int size, u32 *val); > int dw_pcie_write(void __iomem *addr, int size, u32 val); > > -- > 2.17.1
On 4/24/2019 1:43 PM, Gustavo Pimentel wrote: > On Wed, Apr 24, 2019 at 6:19:53, Vidya Sagar <vidyas@nvidia.com> wrote: > >> Move PCIe config space capability search API to common DesignWare file >> as this can be used by both host and ep mode codes. >> >> Signed-off-by: Vidya Sagar <vidyas@nvidia.com> >> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> >> --- >> Changes from [v4]: >> * Removed redundant APIs in pcie-designware-ep.c file after moving them >> to pcie-designware.c file based on Bjorn's comments. >> >> Changes from [v3]: >> * Rebased to linux-next top of the tree >> >> Changes from [v2]: >> * None >> >> Changes from [v1]: >> * Removed dw_pcie_find_next_ext_capability() API from here and made a >> separate patch for that >> >> .../pci/controller/dwc/pcie-designware-ep.c | 37 +----------------- >> drivers/pci/controller/dwc/pcie-designware.c | 39 +++++++++++++++++++ >> drivers/pci/controller/dwc/pcie-designware.h | 2 + >> 3 files changed, 43 insertions(+), 35 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c >> index 2bf5a35c0570..65f479250087 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c >> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c >> @@ -40,39 +40,6 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) >> __dw_pcie_ep_reset_bar(pci, bar, 0); >> } >> >> -static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, >> - u8 cap) >> -{ >> - u8 cap_id, next_cap_ptr; >> - u16 reg; >> - >> - if (!cap_ptr) >> - return 0; >> - >> - reg = dw_pcie_readw_dbi(pci, cap_ptr); >> - cap_id = (reg & 0x00ff); >> - >> - if (cap_id > PCI_CAP_ID_MAX) >> - return 0; >> - >> - if (cap_id == cap) >> - return cap_ptr; >> - >> - next_cap_ptr = (reg & 0xff00) >> 8; >> - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); >> -} >> - >> -static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) >> -{ >> - u8 next_cap_ptr; >> - u16 reg; >> - >> - reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); >> - next_cap_ptr = (reg & 0x00ff); >> - >> - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); >> -} >> - >> static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, >> struct pci_epf_header *hdr) >> { >> @@ -612,9 +579,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) >> dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); >> return -ENOMEM; >> } >> - ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI); >> + ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); >> >> - ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); >> + ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX); >> >> offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); >> if (offset) { >> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c >> index 8e0081ccf83b..ed21e861df82 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.c >> +++ b/drivers/pci/controller/dwc/pcie-designware.c >> @@ -20,6 +20,45 @@ >> #define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4) >> #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29) >> >> +/* >> + * These APIs are different from standard pci_find_*capability() APIs in the >> + * sense that former can only be used post device enumeration as they require >> + * 'struct pci_dev *' pointer whereas these APIs require 'struct dw_pcie *' >> + * pointer and can be used before link up also. >> + */ >> +static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, >> + u8 cap) >> +{ >> + u8 cap_id, next_cap_ptr; >> + u16 reg; >> + >> + if (!cap_ptr) >> + return 0; >> + >> + reg = dw_pcie_readw_dbi(pci, cap_ptr); >> + cap_id = (reg & 0x00ff); >> + >> + if (cap_id > PCI_CAP_ID_MAX) >> + return 0; >> + >> + if (cap_id == cap) >> + return cap_ptr; >> + >> + next_cap_ptr = (reg & 0xff00) >> 8; >> + return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); >> +} >> + >> +u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) >> +{ >> + u8 next_cap_ptr; >> + u16 reg; >> + >> + reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); >> + next_cap_ptr = (reg & 0x00ff); >> + >> + return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); >> +} >> + >> int dw_pcie_read(void __iomem *addr, int size, u32 *val) >> { >> if (!IS_ALIGNED((uintptr_t)addr, size)) { >> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h >> index 9ee98ced1ef6..35160b4ce929 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.h >> +++ b/drivers/pci/controller/dwc/pcie-designware.h >> @@ -248,6 +248,8 @@ struct dw_pcie { >> #define to_dw_pcie_from_ep(endpoint) \ >> container_of((endpoint), struct dw_pcie, ep) >> >> +u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); >> + > > Can you remove this extra line space? In patch 06/15, I added dw_pcie_find_ext_capability() API so that they are grouped together (separated by a blank line) like how dw_pcie_read() and dw_pcie_write() are grouped. > >> int dw_pcie_read(void __iomem *addr, int size, u32 *val); >> int dw_pcie_write(void __iomem *addr, int size, u32 val); >> >> -- >> 2.17.1 > >
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 2bf5a35c0570..65f479250087 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -40,39 +40,6 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) __dw_pcie_ep_reset_bar(pci, bar, 0); } -static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, - u8 cap) -{ - u8 cap_id, next_cap_ptr; - u16 reg; - - if (!cap_ptr) - return 0; - - reg = dw_pcie_readw_dbi(pci, cap_ptr); - cap_id = (reg & 0x00ff); - - if (cap_id > PCI_CAP_ID_MAX) - return 0; - - if (cap_id == cap) - return cap_ptr; - - next_cap_ptr = (reg & 0xff00) >> 8; - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); -} - -static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) -{ - u8 next_cap_ptr; - u16 reg; - - reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); - next_cap_ptr = (reg & 0x00ff); - - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); -} - static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no, struct pci_epf_header *hdr) { @@ -612,9 +579,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n"); return -ENOMEM; } - ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI); + ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); - ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); + ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX); offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); if (offset) { diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 8e0081ccf83b..ed21e861df82 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -20,6 +20,45 @@ #define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4) #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29) +/* + * These APIs are different from standard pci_find_*capability() APIs in the + * sense that former can only be used post device enumeration as they require + * 'struct pci_dev *' pointer whereas these APIs require 'struct dw_pcie *' + * pointer and can be used before link up also. + */ +static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, + u8 cap) +{ + u8 cap_id, next_cap_ptr; + u16 reg; + + if (!cap_ptr) + return 0; + + reg = dw_pcie_readw_dbi(pci, cap_ptr); + cap_id = (reg & 0x00ff); + + if (cap_id > PCI_CAP_ID_MAX) + return 0; + + if (cap_id == cap) + return cap_ptr; + + next_cap_ptr = (reg & 0xff00) >> 8; + return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); +} + +u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) +{ + u8 next_cap_ptr; + u16 reg; + + reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); + next_cap_ptr = (reg & 0x00ff); + + return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); +} + int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if (!IS_ALIGNED((uintptr_t)addr, size)) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 9ee98ced1ef6..35160b4ce929 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -248,6 +248,8 @@ struct dw_pcie { #define to_dw_pcie_from_ep(endpoint) \ container_of((endpoint), struct dw_pcie, ep) +u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); + int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val);