| Message ID | 20190510130855.4263-1-alexandre.belloni@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL | expand |
Hi Alexandre, > This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7. > > The lpc32xx clock driver is not able to actually change the PLL rate as > this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK, > then stop the PLL, update the register, restart the PLL and wait for the > PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK > PLL. > > Currently, the HCLK driver simply updates the registers but this has no > real effect and all the clock rate calculation end up being wrong. This is > especially annoying for the peripheral (e.g. UARTs, I2C, SPI). > > Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Gregory > --- > arch/arm/boot/dts/lpc32xx.dtsi | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi > index 20b38f4ade37..a49c97e5a38a 100644 > --- a/arch/arm/boot/dts/lpc32xx.dtsi > +++ b/arch/arm/boot/dts/lpc32xx.dtsi > @@ -323,9 +323,6 @@ > > clocks = <&xtal_32k>, <&xtal>; > clock-names = "xtal_32k", "xtal"; > - > - assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>; > - assigned-clock-rates = <208000000>; > }; > }; > > -- > 2.21.0 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 20b38f4ade37..a49c97e5a38a 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -323,9 +323,6 @@ clocks = <&xtal_32k>, <&xtal>; clock-names = "xtal_32k", "xtal"; - - assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>; - assigned-clock-rates = <208000000>; }; };
This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7. The lpc32xx clock driver is not able to actually change the PLL rate as this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK, then stop the PLL, update the register, restart the PLL and wait for the PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK PLL. Currently, the HCLK driver simply updates the registers but this has no real effect and all the clock rate calculation end up being wrong. This is especially annoying for the peripheral (e.g. UARTs, I2C, SPI). Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> --- arch/arm/boot/dts/lpc32xx.dtsi | 3 --- 1 file changed, 3 deletions(-)