From patchwork Fri May 17 12:38:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 10947889 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2DC4B14C0 for ; Fri, 17 May 2019 12:39:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1A5612766D for ; Fri, 17 May 2019 12:39:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 08B0027C05; Fri, 17 May 2019 12:39:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9B20A2766D for ; Fri, 17 May 2019 12:39:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=55exHaIT3lV1amSyn2HczUwaRc3Jf5F3Bl5N8bzTKOM=; b=rO7I/M/ezuphA6 +64ZA1GzACwX4H+snz3KP7YZil2Yh/Bum3eMD2XJkYg8Ra0CbOP4A/IJyu+Xp/0YIlfQlCJd/eOPL ec/cwb84WCQW++81U8/VSVg+OMTkd86fH8+HZVAAH9BImckx8g1hWk5Ja7zWabYz0ZWkg1PL4ClBu GlXjt9KX5knAm1sV6wTWjMuCg1iTduOqSCXmDGjnDEhsYdQinDZoSsDQP7yL6XcJ8q4JaTzIubnIY LtS2PzNh54DWbT3a1/e7D5H4SiAUUiT1dOz3iyFHBX2AXj6hi30lNPC3WoFzKGSle5pldI8Yg3rmR cp1/SqrsN+JfcGliSzGQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRc98-0001VA-4c; Fri, 17 May 2019 12:39:34 +0000 Received: from hqemgate15.nvidia.com ([216.228.121.64]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hRc94-0001SR-RI for linux-arm-kernel@lists.infradead.org; Fri, 17 May 2019 12:39:32 +0000 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 17 May 2019 05:38:48 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 17 May 2019 05:39:30 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 17 May 2019 05:39:30 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 17 May 2019 12:39:30 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 17 May 2019 12:39:29 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 17 May 2019 12:39:29 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 17 May 2019 05:39:29 -0700 From: Vidya Sagar To: , , , , , , , , , , Subject: [PATCH V7 02/15] PCI: Disable MSI for Tegra194 root port Date: Fri, 17 May 2019 18:08:33 +0530 Message-ID: <20190517123846.3708-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190517123846.3708-1-vidyas@nvidia.com> References: <20190517123846.3708-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1558096728; bh=HSVuj7isNNLisx5nM09rg6tTu0ozPxsXBWfH15LevhU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=qj/2P0IY9G8DF5KjvSznVd9FT16mrDjVXV0xfi1/7AqJWk4srJu8APDjKeHT3v2kr ISuTzQD8xVe+2gPcABPsZw2y3OE9xe+XQ+JVn57E81k4homBCm7TsIN3ZPljRT454F /J/0VyvZ6Mo/k7SW4vMrTjH5ZRq64JdK7ai6ebnX6Ugr3tqovLUe+i2uM9+diVjjCF 0utAnriSb0poPoBtGIH5lS76uXhFCG2zb8Tci5H30r6gmHSGM4gxGnZSLdZwxKFzY3 5vwgh35nwqUGbHfDJ2RboEi+QBponQxGTDbZ72POiqPzC52K4EwJMxatpH1hcCySu9 cNY71x5qipEOQ== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190517_053930_898203_A5046605 X-CRM114-Status: UNSURE ( 7.84 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com, kthota@nvidia.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, linux-tegra@vger.kernel.org, vidyas@nvidia.com, linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra194 rootports don't generate MSI interrupts for PME events and hence MSI needs to be disabled for them to avoid root ports service drivers registering their respective ISRs with MSI interrupt. Signed-off-by: Vidya Sagar Reviewed-by: Thierry Reding --- Changes since [v6]: * This is a new patch drivers/pci/quirks.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 0f16acc323c6..28f9a0380df5 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2592,6 +2592,20 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15, nvenet_msi_disable); +/* + * Tegra194's PCIe root ports don't generate MSI interrupts for PME events + * instead legacy interrupts are generated. Hence, to avoid service drivers + * registering their respective ISRs for MSIs, need to disable MSI interrupts + * for root ports. + */ +static void disable_tegra194_rp_msi(struct pci_dev *dev) +{ + dev->no_msi = 1; +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, disable_tegra194_rp_msi); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, disable_tegra194_rp_msi); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, disable_tegra194_rp_msi); + /* * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing * config register. This register controls the routing of legacy