@@ -103,6 +103,7 @@
#cooling-cells = <2>;
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
+ cpu-idle-states = <&CPU_SLEEP>;
};
A53_1: cpu@1 {
@@ -115,6 +116,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
};
A53_2: cpu@2 {
@@ -127,6 +129,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
};
A53_3: cpu@3 {
@@ -139,11 +142,27 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
};
A53_L2: l2-cache0 {
compatible = "cache";
};
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010033>;
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+ };
+
};
a53_opp_table: opp-table {
@@ -502,6 +521,7 @@
reg = <0x303a0000 0x10000>;
interrupt-parent = <&gic>;
interrupt-controller;
+ broken-wake-request-signals;
#interrupt-cells = <3>;
pgc {
Add the cpu-sleep idle state with all the necessary parameters and also add the cpu-idle-states to the cpu nodes. The 'broken-wake-request-signals' property is used to let the irq-imx-gpcv2 driver know that the wake request signals from GIC are not linked to the GPC at all and, therefore, the driver should make use of the dedicated workaround to explicitly wake up the target core on every IPI. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)