diff mbox series

[25/59] KVM: arm64: nv: Don't expose SVE to nested guests

Message ID	20190621093843.220980-26-marc.zyngier@arm.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org> From: Marc Zyngier <marc.zyngier@arm.com> To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Subject: [PATCH 25/59] KVM: arm64: nv: Don't expose SVE to nested guests Date: Fri, 21 Jun 2019 10:38:09 +0100 Message-Id: <20190621093843.220980-26-marc.zyngier@arm.com> In-Reply-To: <20190621093843.220980-1-marc.zyngier@arm.com> References: <20190621093843.220980-1-marc.zyngier@arm.com> MIME-Version: 1.0 Precedence: list Cc: Julien Thierry <julien.thierry@arm.com>, Andre Przywara <andre.przywara@arm.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Christoffer Dall <christoffer.dall@arm.com>, Dave Martin <Dave.Martin@arm.com>, James Morse <james.morse@arm.com>, Jintack Lim <jintack@cs.columbia.edu> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org
Series	KVM: arm64: ARMv8.3 Nested Virtualization support \| expand [00/59] KVM: arm64: ARMv8.3 Nested Virtualization support [01/59] KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s [02/59] KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h [03/59] arm64: Add ARM64_HAS_NESTED_VIRT cpufeature [04/59] KVM: arm64: nv: Introduce nested virtualization VCPU feature [05/59] KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set [06/59] KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x [07/59] KVM: arm64: nv: Add EL2 system registers to vcpu context [08/59] KVM: arm64: nv: Reset VMPIDR_EL2 and VPIDR_EL2 to sane values [09/59] KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state [10/59] KVM: arm64: nv: Support virtual EL2 exceptions [11/59] KVM: arm64: nv: Inject HVC exceptions to the virtual EL2 [12/59] KVM: arm64: nv: Handle trapped ERET from virtual EL2 [13/59] KVM: arm64: nv: Handle virtual EL2 registers in vcpu_read/write_sys_reg() [14/59] KVM: arm64: nv: Handle SPSR_EL2 specially [15/59] KVM: arm64: nv: Refactor vcpu_{read,write}_sys_reg [16/59] KVM: arm64: nv: Save/Restore vEL2 sysregs [17/59] KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor [18/59] KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2 [19/59] KVM: arm64: nv: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from virtual EL2 [20/59] KVM: arm64: nv: Trap CPACR_EL1 access in virtual EL2 [21/59] KVM: arm64: nv: Set a handler for the system instruction traps [22/59] KVM: arm64: nv: Handle PSCI call via smc from the guest [23/59] KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting [24/59] KVM: arm64: nv: Respect virtual CPTR_EL2.TFP setting [25/59] KVM: arm64: nv: Don't expose SVE to nested guests [26/59] KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting [27/59] KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings [28/59] KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting [29/59] KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2 [30/59] KVM: arm64: nv: Configure HCR_EL2 for nested virtualization [31/59] KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2 changes [32/59] KVM: arm64: nv: Hide RAS from nested guests [33/59] KVM: arm64: nv: Pretend we only support larger-than-host page sizes [34/59] KVM: arm/arm64: nv: Factor out stage 2 page table data from struct kvm [35/59] KVM: arm/arm64: nv: Support multiple nested stage 2 mmu structures [36/59] KVM: arm64: nv: Implement nested Stage-2 page table walk logic [37/59] KVM: arm64: nv: Handle shadow stage 2 page faults [38/59] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables [39/59] KVM: arm64: nv: Move last_vcpu_ran to be per s2 mmu [40/59] KVM: arm64: nv: Don't always start an S2 MMU search from the beginning [41/59] KVM: arm64: nv: Introduce sys_reg_desc.forward_trap [42/59] KVM: arm64: nv: Rework the system instruction emulation framework [43/59] KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 [44/59] KVM: arm64: nv: Trap and emulate TLBI instructions from virtual EL2 [45/59] KVM: arm64: nv: Handle traps for timer _EL02 and _EL2 sysregs accessors [46/59] KVM: arm64: nv: arch_timer: Support hyp timer emulation [47/59] KVM: arm64: nv: Propagate CNTVOFF_EL2 to the virtual EL1 timer [48/59] KVM: arm64: nv: Load timer before the GIC [49/59] KVM: arm64: nv: vgic-v3: Take cpu_if pointer directly instead of vcpu [50/59] KVM: arm64: nv: Nested GICv3 Support [51/59] KVM: arm64: nv: vgic: Emulate the HW bit in software [52/59] KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ [53/59] KVM: arm64: nv: Implement maintenance interrupt forwarding [54/59] KVM: arm64: nv: Add nested GICv3 tracepoints [55/59] arm64: KVM: nv: Add handling of EL2-specific timer registers [56/59] arm64: KVM: nv: Honor SCTLR_EL2.SPAN on entering vEL2 [57/59] arm64: KVM: nv: Handle SCTLR_EL2 RES0/RES1 bits [58/59] arm64: KVM: nv: Restrict S2 RD/WR permissions to match the guest's [59/59] arm64: KVM: nv: Allow userspace to request KVM_ARM_VCPU_NESTED_VIRT

Commit Message

Marc Zyngier June 21, 2019, 9:38 a.m. UTC

For the time being, pretend that NV and SVE are incompatible.
Things will shortly change... Or not.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm64/kvm/sys_regs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index e711dde4511c..94affa43e86c 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1324,7 +1324,8 @@  static u64 read_id_reg(const struct kvm_vcpu *vcpu,
 			 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
 	u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
 
-	if (id == SYS_ID_AA64PFR0_EL1 && !vcpu_has_sve(vcpu)) {
+	if (id == SYS_ID_AA64PFR0_EL1 &&
+	    (!vcpu_has_sve(vcpu) || nested_virt_in_use(vcpu))) {
 		val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
 	} else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
 		val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |