new file mode 100644
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/freescale/fsl,dsp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8 IPC DSP interface
+
+maintainers:
+ - Daniel Baluta <daniel.baluta@nxp.com>
+
+description: |
+ IPC communication layer between Host CPU and DSP on NXP i.MX8 platforms
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qxp-dsp
+
+ mboxes:
+ description:
+ List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
+ (see mailbox/fsl,mu.txt)
+ maxItems: 4
+
+ mbox-names:
+ items:
+ - const: txdb0
+ - const: txdb1
+ - const: rxdb0
+ - const: rxdb1
+
+required:
+ - compatible
+ - mboxes
+ - mbox-names
+
+examples:
+ - |
+ dsp_ipc {
+ compatbile = "fsl,imx8qxp-dsp";
+ mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
+ mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
+ };
DSP IPC is the layer that allows the Host CPU to communicate with DSP firmware. DSP is part of some i.MX8 boards (e.g i.MX8QM, i.MX8QXP) Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> --- .../devicetree/bindings/dsp/fsl,dsp_ipc.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/dsp/fsl,dsp_ipc.yaml