diff mbox series

[1/4] arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes

Message ID 20190722202024.14867-2-s-anna@ti.com (mailing list archive)
State New, archived
Headers show
Series Add Mailbox nodes for TI K3 AM65x & J721E SoCs | expand

Commit Message

Suman Anna July 22, 2019, 8:20 p.m. UTC
The AM65x Main NavSS block contains a Mailbox IP instance with
multiple clusters. Each cluster is equivalent to an Mailbox IP
instance on OMAP platforms.

Add all the Mailbox clusters as their own nodes under the MAIN
NavSS cbass_main_navss interconnect node instead of creating an
almost empty parent node for the new K3 mailbox IP and the clusters
as its child nodes. All these nodes are marked as disabled, and
they need to be enabled along with the appropriate child nodes
on a need basis.

NOTE:
The NavSS only has a limited number of interrupts, so all the
interrupts generated by a Mailbox IP are not added by default.
Only the needed interrupts that are targeted towards the A53
GIC will need to be be added later on when some sub-mailbox
child nodes are added.

Signed-off-by: Suman Anna <s-anna@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
 1 file changed, 108 insertions(+)

Comments

Nishanth Menon July 23, 2019, 11:35 a.m. UTC | #1
On 15:20-20190722, Suman Anna wrote:
> The AM65x Main NavSS block contains a Mailbox IP instance with
> multiple clusters. Each cluster is equivalent to an Mailbox IP
> instance on OMAP platforms.
> 
> Add all the Mailbox clusters as their own nodes under the MAIN
> NavSS cbass_main_navss interconnect node instead of creating an
> almost empty parent node for the new K3 mailbox IP and the clusters
> as its child nodes. All these nodes are marked as disabled, and
> they need to be enabled along with the appropriate child nodes
> on a need basis.
> 
> NOTE:
> The NavSS only has a limited number of interrupts, so all the
> interrupts generated by a Mailbox IP are not added by default.
> Only the needed interrupts that are targeted towards the A53
> GIC will need to be be added later on when some sub-mailbox
> child nodes are added.
> 
> Signed-off-by: Suman Anna <s-anna@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index 8413e80f9d3a..0b3ea2a871ee 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -419,6 +419,114 @@
>  			reg = <0x00 0x30e00000 0x00 0x1000>;
>  			#hwlock-cells = <1>;
>  		};
> +
> +		mailbox0_cluster0: mailbox@31f80000 {
> +			compatible = "ti,am654-mailbox";
> +			reg = <0x00 0x31f80000 0x00 0x200>;
> +			#mbox-cells = <1>;
> +			ti,mbox-num-users = <4>;
> +			ti,mbox-num-fifos = <16>;
> +			status = "disabled";

We don't use status="disabled" as default so far.
Suman Anna July 23, 2019, 5:50 p.m. UTC | #2
Hi Nishanth,

On 7/23/19 6:35 AM, Nishanth Menon wrote:
> On 15:20-20190722, Suman Anna wrote:
>> The AM65x Main NavSS block contains a Mailbox IP instance with
>> multiple clusters. Each cluster is equivalent to an Mailbox IP
>> instance on OMAP platforms.
>>
>> Add all the Mailbox clusters as their own nodes under the MAIN
>> NavSS cbass_main_navss interconnect node instead of creating an
>> almost empty parent node for the new K3 mailbox IP and the clusters
>> as its child nodes. All these nodes are marked as disabled, and
>> they need to be enabled along with the appropriate child nodes
>> on a need basis.
>>
>> NOTE:
>> The NavSS only has a limited number of interrupts, so all the
>> interrupts generated by a Mailbox IP are not added by default.
>> Only the needed interrupts that are targeted towards the A53
>> GIC will need to be be added later on when some sub-mailbox
>> child nodes are added.
>>
>> Signed-off-by: Suman Anna <s-anna@ti.com>
>> ---
>>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
>>  1 file changed, 108 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> index 8413e80f9d3a..0b3ea2a871ee 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
>> @@ -419,6 +419,114 @@
>>  			reg = <0x00 0x30e00000 0x00 0x1000>;
>>  			#hwlock-cells = <1>;
>>  		};
>> +
>> +		mailbox0_cluster0: mailbox@31f80000 {
>> +			compatible = "ti,am654-mailbox";
>> +			reg = <0x00 0x31f80000 0x00 0x200>;
>> +			#mbox-cells = <1>;
>> +			ti,mbox-num-users = <4>;
>> +			ti,mbox-num-fifos = <16>;
>> +			status = "disabled";
> 
> We don't use status="disabled" as default so far.
> 

For the OMAP mailboxes, we do not want to enable just the cluster. A
cluster without any enabled sub-mailboxes or interrupts will fail the probe.

There are 12 clusters but we won't be enabling all clusters for the MPU
core running Linux. There are some clusters that are dedicated to
RTOS-to-RTOS IPC which we don't want to even probe on Linux. This patch
adds all the clusters, and the next patch enables only the clusters used
by Linux that have the proper sub-mailboxes and interrupts. Please see
the NOTE above for the reason why not all the 4 interrupts from each
cluster are added here.

regards
Suman
Nishanth Menon July 23, 2019, 10:10 p.m. UTC | #3
On 12:50-20190723, Suman Anna wrote:
> For the OMAP mailboxes, we do not want to enable just the cluster. A
> cluster without any enabled sub-mailboxes or interrupts will fail the probe.
> 
> There are 12 clusters but we won't be enabling all clusters for the MPU
> core running Linux. There are some clusters that are dedicated to
> RTOS-to-RTOS IPC which we don't want to even probe on Linux. This patch
> adds all the clusters, and the next patch enables only the clusters used
> by Linux that have the proper sub-mailboxes and interrupts. Please see
> the NOTE above for the reason why not all the 4 interrupts from each
> cluster are added here.

Please follow the example of uart and disable in the board file. Please
see existing code when posting new nodes.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 8413e80f9d3a..0b3ea2a871ee 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -419,6 +419,114 @@ 
 			reg = <0x00 0x30e00000 0x00 0x1000>;
 			#hwlock-cells = <1>;
 		};
+
+		mailbox0_cluster0: mailbox@31f80000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f80000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster1: mailbox@31f81000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f81000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster2: mailbox@31f82000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f82000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster3: mailbox@31f83000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f83000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster4: mailbox@31f84000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f84000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster5: mailbox@31f85000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f85000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster6: mailbox@31f86000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f86000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster7: mailbox@31f87000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f87000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster8: mailbox@31f88000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f88000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster9: mailbox@31f89000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f89000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster10: mailbox@31f8a000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8a000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
+
+		mailbox0_cluster11: mailbox@31f8b000 {
+			compatible = "ti,am654-mailbox";
+			reg = <0x00 0x31f8b000 0x00 0x200>;
+			#mbox-cells = <1>;
+			ti,mbox-num-users = <4>;
+			ti,mbox-num-fifos = <16>;
+			status = "disabled";
+		};
 	};
 
 	main_gpio0:  main_gpio0@600000 {