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Mon, 22 Jul 2019 15:20:38 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 22 Jul 2019 15:20:38 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6MKKcUB099967; Mon, 22 Jul 2019 15:20:38 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6MKKcZ21510; Mon, 22 Jul 2019 15:20:38 -0500 (CDT) From: Suman Anna To: Tero Kristo , Nishanth Menon Subject: [PATCH 2/4] arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs Date: Mon, 22 Jul 2019 15:20:22 -0500 Message-ID: <20190722202024.14867-3-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190722202024.14867-1-s-anna@ti.com> References: <20190722202024.14867-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190722_132040_143186_C840B850 X-CRM114-Status: GOOD ( 12.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add the sub-mailbox nodes that are used to communicate between MPU and the two R5F remote processors present in the MCU domain. The parent mailbox cluster nodes are enabled and the interrupts associated with the Mailbox Cluster User interrupt used by the sub-mailbox nodes are also added. The GIC_SPI interrupt to be used is dynamically allocated and managed by the System Firmware through the ti-sci-intr irqchip driver. The sub-mailbox nodes utilize the System Mailbox clusters 1 and 2. These sub-mailbox nodes are added to match the hard-coded mailbox configuration used within the TI RTOS IPC software packages. The Cortex R5F processor sub-system is assumed to be running in Split mode, so a sub-mailbox node is used by each of the R5F cores. Only the sub-mailbox node from cluster 0 is used in case of Lockstep mode. Signed-off-by: Suman Anna --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 0b3ea2a871ee..317563c995b1 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -426,7 +426,13 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; - status = "disabled"; + interrupt-parent = <&intr_main_navss>; + interrupts = <164 0>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-tx = <1 0 0>; + ti,mbox-rx = <0 0 0>; + }; }; mailbox0_cluster1: mailbox@31f81000 { @@ -435,7 +441,13 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; - status = "disabled"; + interrupt-parent = <&intr_main_navss>; + interrupts = <165 0>; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-tx = <1 0 0>; + ti,mbox-rx = <0 0 0>; + }; }; mailbox0_cluster2: mailbox@31f82000 {