| Message ID | 20190723115545.1506-1-marc.zyngier@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [BOOTWRAPPER] Make GICv3.1 extended ranges available to non-secure | expand |
Hi Marc, On Tue, Jul 23, 2019 at 12:55:45PM +0100, Marc Zyngier wrote: > If we have a GICv3.1-capable system, configure the EPPI/ESPI ranges > to be accessible from the non-secure world. > > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> > --- > gic-v3.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > > diff --git a/gic-v3.c b/gic-v3.c > index 476f703..4b733ba 100644 > --- a/gic-v3.c > +++ b/gic-v3.c > @@ -17,6 +17,8 @@ > #define GICD_TYPER 0x4 > #define GICD_IGROUP0 0x80 > #define GICD_IGRPMOD0 0xd00 > +#define GICD_IGROUPR0E 0x1000 > +#define GICD_IGRPMODR0E 0x3400 > > #define GICD_CTLR_EnableGrp0 (1 << 0) > #define GICD_CTLR_EnableGrp1ns (1 << 1) > @@ -57,6 +59,7 @@ void gic_secure_init_primary(void) > * ChildrenAsleep to be 0. > */ > uint32_t waker = raw_readl(gicr_ptr + GICR_WAKER); > + uint32_t regs; > waker &= ~GICR_WAKER_ProcessorSleep; > raw_writel(waker, gicr_ptr + GICR_WAKER); > dsb(st); > @@ -72,8 +75,11 @@ void gic_secure_init_primary(void) > typer = raw_readl(gicr_ptr + GICR_TYPER); > > gicr_ptr += 0x10000; /* Go to SGI_Base */ > - raw_writel(~0x0, gicr_ptr + GICR_IGROUP0); > - raw_writel(0x0, gicr_ptr + GICR_IGRPMOD0); > + regs = 1 + ((typer >> 27) & 0x1f); IIUC that's GICR_TYPER.PPInum, right? > + for (i = 0; i < regs; i++) { > + raw_writel(~0x0, gicr_ptr + GICR_IGROUP0 + i * 4); > + raw_writel(0x0, gicr_ptr + GICR_IGRPMOD0 + i * 4); > + } > > /* Next redist */ > gicr_ptr += 0x10000; > @@ -87,6 +93,10 @@ void gic_secure_init_primary(void) > raw_writel(~0x0, gicd_base + GICD_IGROUP0 + i * 4); > raw_writel(0x0, gicd_base + GICD_IGRPMOD0 + i * 4); > } > + for (i = 0; i < ((typer >> 27) & GICD_TYPER_ITLineNumber); i++) { IIUC this is ESPI_range_field, so using the GICD_TYPER_ITLineNumber mnemonic is a bit misleading. Given the verbose regfield names, _SHIFT and _MASK definitions will make this illegible, so could we please add extactors: #define GICR_TYPER_PPInum(r) (((r) >> 27) & 0x1f) #define GICD_TYPER_ESPI_range(r) (((r) >> 27) & 0x1f) ... and use those in the for loops? With that, this looks good to me. If you respin, I'm happy to pick this up. :) Thanks, Mark. > + raw_writel(~0x0, gicd_base + GICD_IGROUPR0E + i * 4); > + raw_writel(0x0, gicd_base + GICD_IGRPMODR0E + i * 4); > + } > } > > void gic_secure_init(void) > -- > 2.18.0 >
On 23/07/2019 15:10, Mark Rutland wrote: > Hi Marc, > > On Tue, Jul 23, 2019 at 12:55:45PM +0100, Marc Zyngier wrote: >> If we have a GICv3.1-capable system, configure the EPPI/ESPI ranges >> to be accessible from the non-secure world. >> >> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> >> --- >> gic-v3.c | 14 ++++++++++++-- >> 1 file changed, 12 insertions(+), 2 deletions(-) >> >> diff --git a/gic-v3.c b/gic-v3.c >> index 476f703..4b733ba 100644 >> --- a/gic-v3.c >> +++ b/gic-v3.c >> @@ -17,6 +17,8 @@ >> #define GICD_TYPER 0x4 >> #define GICD_IGROUP0 0x80 >> #define GICD_IGRPMOD0 0xd00 >> +#define GICD_IGROUPR0E 0x1000 >> +#define GICD_IGRPMODR0E 0x3400 >> >> #define GICD_CTLR_EnableGrp0 (1 << 0) >> #define GICD_CTLR_EnableGrp1ns (1 << 1) >> @@ -57,6 +59,7 @@ void gic_secure_init_primary(void) >> * ChildrenAsleep to be 0. >> */ >> uint32_t waker = raw_readl(gicr_ptr + GICR_WAKER); >> + uint32_t regs; >> waker &= ~GICR_WAKER_ProcessorSleep; >> raw_writel(waker, gicr_ptr + GICR_WAKER); >> dsb(st); >> @@ -72,8 +75,11 @@ void gic_secure_init_primary(void) >> typer = raw_readl(gicr_ptr + GICR_TYPER); >> >> gicr_ptr += 0x10000; /* Go to SGI_Base */ >> - raw_writel(~0x0, gicr_ptr + GICR_IGROUP0); >> - raw_writel(0x0, gicr_ptr + GICR_IGRPMOD0); >> + regs = 1 + ((typer >> 27) & 0x1f); > > IIUC that's GICR_TYPER.PPInum, right? Indeed. > >> + for (i = 0; i < regs; i++) { >> + raw_writel(~0x0, gicr_ptr + GICR_IGROUP0 + i * 4); >> + raw_writel(0x0, gicr_ptr + GICR_IGRPMOD0 + i * 4); >> + } >> >> /* Next redist */ >> gicr_ptr += 0x10000; >> @@ -87,6 +93,10 @@ void gic_secure_init_primary(void) >> raw_writel(~0x0, gicd_base + GICD_IGROUP0 + i * 4); >> raw_writel(0x0, gicd_base + GICD_IGRPMOD0 + i * 4); >> } >> + for (i = 0; i < ((typer >> 27) & GICD_TYPER_ITLineNumber); i++) { > > IIUC this is ESPI_range_field, so using the GICD_TYPER_ITLineNumber > mnemonic is a bit misleading. > > Given the verbose regfield names, _SHIFT and _MASK definitions will make > this illegible, so could we please add extactors: > > #define GICR_TYPER_PPInum(r) (((r) >> 27) & 0x1f) > #define GICD_TYPER_ESPI_range(r) (((r) >> 27) & 0x1f) > > ... and use those in the for loops? > > With that, this looks good to me. If you respin, I'm happy to pick this > up. :) Sure, I'll do that shortly. Thanks, M.
diff --git a/gic-v3.c b/gic-v3.c index 476f703..4b733ba 100644 --- a/gic-v3.c +++ b/gic-v3.c @@ -17,6 +17,8 @@ #define GICD_TYPER 0x4 #define GICD_IGROUP0 0x80 #define GICD_IGRPMOD0 0xd00 +#define GICD_IGROUPR0E 0x1000 +#define GICD_IGRPMODR0E 0x3400 #define GICD_CTLR_EnableGrp0 (1 << 0) #define GICD_CTLR_EnableGrp1ns (1 << 1) @@ -57,6 +59,7 @@ void gic_secure_init_primary(void) * ChildrenAsleep to be 0. */ uint32_t waker = raw_readl(gicr_ptr + GICR_WAKER); + uint32_t regs; waker &= ~GICR_WAKER_ProcessorSleep; raw_writel(waker, gicr_ptr + GICR_WAKER); dsb(st); @@ -72,8 +75,11 @@ void gic_secure_init_primary(void) typer = raw_readl(gicr_ptr + GICR_TYPER); gicr_ptr += 0x10000; /* Go to SGI_Base */ - raw_writel(~0x0, gicr_ptr + GICR_IGROUP0); - raw_writel(0x0, gicr_ptr + GICR_IGRPMOD0); + regs = 1 + ((typer >> 27) & 0x1f); + for (i = 0; i < regs; i++) { + raw_writel(~0x0, gicr_ptr + GICR_IGROUP0 + i * 4); + raw_writel(0x0, gicr_ptr + GICR_IGRPMOD0 + i * 4); + } /* Next redist */ gicr_ptr += 0x10000; @@ -87,6 +93,10 @@ void gic_secure_init_primary(void) raw_writel(~0x0, gicd_base + GICD_IGROUP0 + i * 4); raw_writel(0x0, gicd_base + GICD_IGRPMOD0 + i * 4); } + for (i = 0; i < ((typer >> 27) & GICD_TYPER_ITLineNumber); i++) { + raw_writel(~0x0, gicd_base + GICD_IGROUPR0E + i * 4); + raw_writel(0x0, gicd_base + GICD_IGRPMODR0E + i * 4); + } } void gic_secure_init(void)
If we have a GICv3.1-capable system, configure the EPPI/ESPI ranges to be accessible from the non-secure world. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- gic-v3.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-)