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[91.78.220.99]) by smtp.gmail.com with ESMTPSA id i13sm58897736wrr.73.2019.07.30.10.10.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 30 Jul 2019 10:10:07 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , "Rafael J. Wysocki" , Daniel Lezcano Subject: [PATCH v4 02/13] ARM: tegra: Change tegra_set_cpu_in_lp2() type to void Date: Tue, 30 Jul 2019 20:09:44 +0300 Message-Id: <20190730170955.11987-3-digetx@gmail.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190730170955.11987-1-digetx@gmail.com> References: <20190730170955.11987-1-digetx@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190730_101011_105267_B52529B8 X-CRM114-Status: GOOD ( 12.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The old Tegra30 CPUIDLE driver had intention to check whether primary CPU was the last CPU that entered LP2 (CC6) idle-state, but that functionality never got utilized by the old-removed driver because it never supported the CC6 while secondary CPUs were online. The new driver will properly support CC6 on Tegra30, including the case where secondary CPUs are online, and that knowledge about what CPUs entered CC6 won't be needed at all because new driver will use different approach by making use of the coupled idle-state and explicitly parking secondary CPUs before entering into CC6. Signed-off-by: Dmitry Osipenko --- arch/arm/mach-tegra/pm.c | 8 +------- arch/arm/mach-tegra/pm.h | 2 +- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 6aaacb5757e1..2f6fb54be9f8 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -123,11 +123,9 @@ void tegra_clear_cpu_in_lp2(void) spin_unlock(&tegra_lp2_lock); } -bool tegra_set_cpu_in_lp2(void) +void tegra_set_cpu_in_lp2(void) { int phy_cpu_id = cpu_logical_map(smp_processor_id()); - bool last_cpu = false; - cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask; u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; spin_lock(&tegra_lp2_lock); @@ -135,11 +133,7 @@ bool tegra_set_cpu_in_lp2(void) BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id))); *cpu_in_lp2 |= BIT(phy_cpu_id); - if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) - last_cpu = true; - spin_unlock(&tegra_lp2_lock); - return last_cpu; } static int tegra_sleep_cpu(unsigned long v2p) diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 1e51a9b636eb..3f3164ad04b7 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -24,7 +24,7 @@ void tegra30_lp1_iram_hook(void); void tegra30_sleep_core_init(void); void tegra_clear_cpu_in_lp2(void); -bool tegra_set_cpu_in_lp2(void); +void tegra_set_cpu_in_lp2(void); void tegra_idle_lp2_last(void); extern void (*tegra_tear_down_cpu)(void);