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Mon, 12 Aug 2019 14:21:39 +0000 From: Philippe Schenker To: Marcel Ziswiler , Max Krummenacher , "stefan@agner.ch" , "devicetree@vger.kernel.org" , Rob Herring , Shawn Guo , Mark Rutland , =?iso-8859-2?q?Michal_Vok=E1=E8?= , Fabio Estevam Subject: [PATCH v4 15/21] ARM: dts: imx6ull-colibri: reduce v_batt current in power off Thread-Topic: [PATCH v4 15/21] ARM: dts: imx6ull-colibri: reduce v_batt current in power off Thread-Index: AQHVURlBuMVOeqxvH0CXDzr0Xq36VA== Date: Mon, 12 Aug 2019 14:21:39 +0000 Message-ID: <20190812142105.1995-16-philippe.schenker@toradex.com> References: <20190812142105.1995-1-philippe.schenker@toradex.com> In-Reply-To: <20190812142105.1995-1-philippe.schenker@toradex.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P194CA0055.EURP194.PROD.OUTLOOK.COM (2603:10a6:803:3c::44) To VI1PR0502MB3965.eurprd05.prod.outlook.com (2603:10a6:803:23::29) authentication-results: spf=none (sender IP is ) smtp.mailfrom=philippe.schenker@toradex.com; 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This switches off SoC internal pull resistors which are provided on the module for TAMPER7 and TAMPER9 SoC pin and switches on a pull down instead of a pullup for the USBC_DET module pin (TAMPER2). Signed-off-by: Max Krummenacher Signed-off-by: Philippe Schenker Acked-by: Marcel Ziswiler Reviewed-by: Oleksandr Suvorov --- Changes in v4: - Add Marcel Ziswiler's Ack Changes in v3: None Changes in v2: None arch/arm/boot/dts/imx6ull-colibri.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 1019ce69a242..1f112ec55e5c 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -533,19 +533,19 @@ pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */ fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0 >; }; pinctrl_snvs_reg_sd: snvs-reg-sd-grp { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0 + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0 >; }; pinctrl_snvs_usbc_det: snvs-usbc-det-grp { fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0 >; };