| Message ID | 20190819205720.24457-9-mike.leach@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: etm4x: Fixes and updates for sysfs API | expand |
On Mon, Aug 19, 2019 at 09:57:20PM +0100, Mike Leach wrote: > Update existing docs for new sysfs API features. > Add new ETMv4 reference document for sysfs programming. > Move coresight documentation to common directory. Please split in 3 different patches. When sending again make sure to add Jonathan Corbet, Greg KH and the linux-doc mailing as recipients. Thanks, Mathieu > > Signed-off-by: Mike Leach <mike.leach@linaro.org> > --- > .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++--- > .../{ => coresight}/coresight-cpu-debug.txt | 0 > .../coresight/coresight-etm4x-reference.txt | 459 ++++++++++++++++++ > .../trace/{ => coresight}/coresight.txt | 0 > MAINTAINERS | 3 +- > 5 files changed, 575 insertions(+), 70 deletions(-) > rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%) > create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt > rename Documentation/trace/{ => coresight}/coresight.txt (100%) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > index 36258bc1b473..112c50ae9986 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > @@ -1,4 +1,4 @@ > -What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source > +What: /sys/bus/coresight/devices/etm<N>/enable_source > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > @@ -8,82 +8,82 @@ Description: (RW) Enable/disable tracing on this specific trace entiry. > of coresight components linking the source to the sink is > configured and managed automatically by the coresight framework. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cpu > +What: /sys/bus/coresight/devices/etm<N>/cpu > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) The CPU this tracing entity is associated with. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp > +What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of PE comparator inputs that are > available for tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp > +What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of address comparator pairs that are > available for tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr > +What: /sys/bus/coresight/devices/etm<N>/nr_cntr > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of counters that are available for > tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp > +What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates how many external inputs are implemented. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc > +What: /sys/bus/coresight/devices/etm<N>/numcidc > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of Context ID comparators that are > available for tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc > +What: /sys/bus/coresight/devices/etm<N>/numvmidc > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of VMID comparators that are available > for tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate > +What: /sys/bus/coresight/devices/etm<N>/nrseqstate > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of sequencer states that are > implemented. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource > +What: /sys/bus/coresight/devices/etm<N>/nr_resource > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of resource selection pairs that are > available for tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp > +What: /sys/bus/coresight/devices/etm<N>/nr_ss_cmp > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of single-shot comparator controls that > are available for tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/reset > +What: /sys/bus/coresight/devices/etm<N>/reset > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (W) Cancels all configuration on a trace unit and set it back > to its boot configuration. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mode > +What: /sys/bus/coresight/devices/etm<N>/mode > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > @@ -91,302 +91,349 @@ Description: (RW) Controls various modes supported by this ETM, for example > P0 instruction tracing, branch broadcast, cycle counting and > context ID tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/pe > +What: /sys/bus/coresight/devices/etm<N>/pe > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls which PE to trace. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event > +What: /sys/bus/coresight/devices/etm<N>/event > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren > +What: /sys/bus/coresight/devices/etm<N>/event_instren > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls the behavior of the events in bank 0 to 3. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts > +What: /sys/bus/coresight/devices/etm<N>/event_ts > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls the insertion of global timestamps in the trace > streams. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq > +What: /sys/bus/coresight/devices/etm<N>/syncfreq > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls how often trace synchronization requests occur. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold > +What: /sys/bus/coresight/devices/etm<N>/cyc_threshold > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Sets the threshold value for cycle counting. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl > +What: /sys/bus/coresight/devices/etm<N>/bb_ctrl > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls which regions in the memory map are enabled to > use branch broadcasting. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_vinst > +What: /sys/bus/coresight/devices/etm<N>/event_vinst > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls instruction trace filtering. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst > +What: /sys/bus/coresight/devices/etm<N>/s_exlevel_vinst > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) In Secure state, each bit controls whether instruction > tracing is enabled for the corresponding exception level. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst > +What: /sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) In non-secure state, each bit controls whether instruction > tracing is enabled for the corresponding exception level. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_idx > +What: /sys/bus/coresight/devices/etm<N>/addr_idx > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Select which address comparator or pair (of comparators) to > work with. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype > +What: /sys/bus/coresight/devices/etm<N>/addr_instdatatype > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls what type of comparison the trace unit performs. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_single > +What: /sys/bus/coresight/devices/etm<N>/addr_single > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Used to setup single address comparator values. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_range > +What: /sys/bus/coresight/devices/etm<N>/addr_range > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Used to setup address range comparator values. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_idx > +What: /sys/bus/coresight/devices/etm<N>/seq_idx > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Select which sequensor. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state > +What: /sys/bus/coresight/devices/etm<N>/seq_state > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Use this to set, or read, the sequencer state. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_event > +What: /sys/bus/coresight/devices/etm<N>/seq_event > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Moves the sequencer state to a specific state. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event > +What: /sys/bus/coresight/devices/etm<N>/seq_reset_event > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Moves the sequencer to state 0 when a programmed event > occurs. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx > +What: /sys/bus/coresight/devices/etm<N>/cntr_idx > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Select which counter unit to work with. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr > +What: /sys/bus/coresight/devices/etm<N>/cntrldvr > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) This sets or returns the reload count value of the > specific counter. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_val > +What: /sys/bus/coresight/devices/etm<N>/cntr_val > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) This sets or returns the current count value of the > specific counter. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl > +What: /sys/bus/coresight/devices/etm<N>/cntr_ctrl > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls the operation of the selected counter. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/res_idx > +What: /sys/bus/coresight/devices/etm<N>/res_idx > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Select which resource selection unit to work with. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl > +What: /sys/bus/coresight/devices/etm<N>/res_ctrl > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls the selection of the resources in the trace unit. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx > +What: /sys/bus/coresight/devices/etm<N>/ctxid_idx > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Select which context ID comparator to work with. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid > +What: /sys/bus/coresight/devices/etm<N>/ctxid_pid > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Get/Set the context ID comparator value to trigger on. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks > +What: /sys/bus/coresight/devices/etm<N>/ctxid_masks > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Mask for all 8 context ID comparator value > registers (if implemented). > > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx > +What: /sys/bus/coresight/devices/etm<N>/vmid_idx > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Select which virtual machine ID comparator to work with. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_val > +What: /sys/bus/coresight/devices/etm<N>/vmid_val > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Get/Set the virtual machine ID comparator value to > trigger on. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks > +What: /sys/bus/coresight/devices/etm<N>/vmid_masks > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Mask for all 8 virtual machine ID comparator value > registers (if implemented). > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr > +What: /sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (RW) Set the Exception Level matching bits for secure and > + non-secure exception levels. > + > +What: /sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (RW) Access the start stop control register for PE input > + comparators. > + > +What: /sys/bus/coresight/devices/etm<N>/addr_cmp_view > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (R) Print the current settings for the selected address > + comparator. > + > +What: /sys/bus/coresight/devices/etm<N>/sshot_idx > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (RW) Select the single shot control register to access. > + > +What: /sys/bus/coresight/devices/etm<N>/sshot_ctrl > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (RW) Access the selected single shot control register. > + > +What: /sys/bus/coresight/devices/etm<N>/sshot_status > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (R) Print the current value of the selected single shot > + status register. > + > +What: /sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (RW) Access the selected single show PE comparator control > + register. > + > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the OS Lock Status Register (0x304). > The value it taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Power Down Control Register > (0x310). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Power Down Status Register > (0x314). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trclsr > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the SW Lock Status Register > (0xFB4). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Authentication Status Register > (0xFB8). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevid > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Device ID Register > (0xFC8). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Device Type Register > (0xFCC). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0 > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Peripheral ID0 Register > (0xFE0). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1 > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Peripheral ID1 Register > (0xFE4). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2 > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Peripheral ID2 Register > (0xFE8). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3 > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Peripheral ID3 Register > (0xFEC). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcconfig > Date: February 2016 > KernelVersion: 4.07 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the trace configuration register > (0x010) as currently set by SW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trctraceid > Date: February 2016 > KernelVersion: 4.07 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the trace ID register (0x040). > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr0 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). > The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr1 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). > The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr2 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > @@ -394,7 +441,7 @@ Description: (R) Returns the maximum size of the data value, data address, > VMID, context ID and instuction address in the trace unit > (0x1E8). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr3 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > @@ -403,42 +450,42 @@ Description: (R) Returns the value associated with various resources > architecture specification for more details (0x1E8). > The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr4 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns how many resources the trace unit supports (0x1F0). > The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr5 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns how many resources the trace unit supports (0x1F4). > The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr8 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns the maximum speculation depth of the instruction > trace stream. (0x180). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr9 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns the number of P0 right-hand keys that the trace unit > can use (0x184). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr10 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns the number of P1 right-hand keys that the trace unit > can use (0x188). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr11 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > @@ -446,7 +493,7 @@ Description: (R) Returns the number of special P1 right-hand keys that the > trace unit can use (0x18C). The value is taken directly from > the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr12 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > @@ -454,7 +501,7 @@ Description: (R) Returns the number of conditional P1 right-hand keys that > the trace unit can use (0x190). The value is taken directly > from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr13 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight/coresight-cpu-debug.txt > similarity index 100% > rename from Documentation/trace/coresight-cpu-debug.txt > rename to Documentation/trace/coresight/coresight-cpu-debug.txt > diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.txt b/Documentation/trace/coresight/coresight-etm4x-reference.txt > new file mode 100644 > index 000000000000..72e81bbbef43 > --- /dev/null > +++ b/Documentation/trace/coresight/coresight-etm4x-reference.txt > @@ -0,0 +1,459 @@ > +ETMv4 sysfs linux driver programming reference - v2. > +==================================================== > + > +Supplement to existing ETMv4 driver documentation. > + > +Sysfs files and directories > +--------------------------- > + > +Root: /sys/bus/coresight/devices/etm<N> > + > + > +The following paragraphs explain the association between sysfs files and the > +ETMv4 registers that they effect. Note the register names are given without > +the ‘TRC’ prefix. > + > +File : mode (rw) > +Trace Registers : {CONFIGR + others} > +Notes : Bit select trace features. See ‘mode’ section below. Bits > + in this will cause equivalent programming of trace config and > + other registers to enable the features requested. > +Syntax & eg : 'echo bitfield > mode' > + bitfield up to 32 bits setting trace features. > +Example : $> echo 0x > mode > + > +File : reset (wo) > +Trace Registers : All > +Notes : Reset all programming to trace nothing / no logic programmed. > +Syntax : 'echo 1 > reset' > + > +File : enable_source (wo) > +Trace Registers : PRGCTLR, All hardware regs. > +Notes : >0: Programs up the hardware with the current values held in > + the driver and enables trace. > + 0: disable trace hardware. > +Syntax : 'echo 1 > enable_source' > + > +File : cpu (ro) > +Trace Registers : None. > +Notes : CPU ID that this ETM is attached to. > +Example :$> cat cpu > + $> 0 > + > +File : addr_idx (rw) > +Trace Registers : None. > +Notes : Virtual register to index address comparator and range > + features. Set index for first of the pair in a range. > +Syntax : 'echo idx > addr_idx' > + Where idx < nr_addr_cmp x 2 > + > +File : addr_range (rw) > +Trace Registers : ACVR[idx, idx+1], VIIECTLR > +Notes : Pair of addresses for a range selected by addr_idx. Include > + / exclude according to the optional parameter, or if omitted > + uses the current ‘mode’ setting. Select comparator range in > + control register. Error if index is odd value. > +Depends : mode, addr_idx > +Syntax : 'echo addr1 addr2 [exclude] > addr_range' > + Where addr1 and addr2 define the range and addr1 < addr2. > + Optional exclude value - 0 for include, 1 for exclude. > +Example : $> echo 0x0000 0x2000 0 > addr_range > + > +File : addr_single (rw) > +Trace Registers : ACVR[idx] > +Notes : Set a single address comparator according to addr_idx. This > + is used if the address comparator is used as part of event > + generation logic etc. > +Depends : addr_idx > +Syntax : 'echo addr1 > addr_single' > + > +File : addr_start (rw) > +Trace Registers : ACVR[idx], VISSCTLR > +Notes : Set a trace start address comparator according to addr_idx. > + Select comparator in control register. > +Depends : addr_idx > +Syntax : 'echo addr1 > addr_start' > + > +File : addr_stop (rw) > +Trace Registers : ACVR[idx], VISSCTLR > +Notes : Set a trace stop address comparator according to addr_idx. > + Select comparator in control register. > +Depends : addr_idx > +Syntax : 'echo addr1 > addr_stop' > + > +File : addr_context (rw) > +Trace Registers : ACATR[idx,{6:4}] > +Notes : Link context ID comparator to address comparator addr_idx > +Depends : addr_idx. > +Syntax : 'echo ctxt_idx > addr_context' > + Where ctxt_idx is the index of the linked context id / vmid > + comparator. > + > +File : addr_ctxtype (rw) > +Trace Registers : ACATR[idx,{3:2}] > +Notes : Input value string. Set type for linked context ID comparator > +Depends : addr_idx > +Syntax : 'echo type > addr_ctxtype' > + Type one of {all, vmid, ctxid, none} > +Example : $> echo ctxid > addr_ctxtype > + > +File : addr_exlevel_s_ns (rw) > +Trace Registers : ACATR[idx,{14:8}] > +Notes : Set the ELx secure and non-secure matching bits for the > + selected address comparator > +Depends : addr_idx > +Syntax : 'echo val > addr_exlevel_s_ns' > + val is a 7 bit value for exception levels to exclude. Input > + value shifted to correct bits in register. > +Example : $> echo 0x4F > addr_exlevel_s_ns > + > +File : addr_instdatatype (rw) > +Trace Registers : ACATR[idx,{1:0}] > +Notes : Set the comparator address type for matching. Driver only > + supports setting instruction address type. > +Depends : addr_idx > + > +File : addr_cmp_view (ro) > +Trace Registers : ACVR[idx, idx+1], ACATR[idx], VIIECTLR > +Notes : Read the currently selected address comparator. If part of > + address range then display both addresses. > +Depends : addr_idx > +Syntax : 'cat addr_cmp_view' > +Example : $> cat addr_cmp_view > + addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00) > + > +File : nr_addr_cmp (ro) > +Trace Registers : From IDR4 > +Notes : Number of address comparator pairs > + > +File : sshot_idx (rw) > +Trace Registers : None > +Notes : Select single shot register set. > + > +File : sshot_ctrl (rw) > +Trace Registers : SSCCR[idx] > +Notes : Access a single shot comparator control register. > +Depends : sshot_idx > +Syntax : 'echo val > sshot_ctrl' > + Writes val into the selected control register. > + > +File : sshot_status (ro) > +Trace Registers : SSCSR[idx] > +Notes : Read a single shot comparator status register > +Depends : sshot_idx > +Syntax : 'cat sshot_status' > + Read status. > +Example : $> cat sshot_status > + 0x1 > + > +File : sshot_pe_ctrl (rw) > +Trace Registers : SSPCICR[idx] > +Notes : Access a single shot PE comparator input control register. > +Depends : sshot_idx > +Syntax : echo val > sshot_pe_ctrl > + Writes val into the selected control register. > + > +File : ns_exlevel_vinst (rw) > +Trace Registers : VICTLR{23:20} > +Notes : Program non-secure exception level filters. Set / clear NS > + exception filter bits. Setting ‘1’ excludes trace from the > + exception level. > +Syntax : 'echo bitfield > ns_exlevel_viinst' > + Where bitfield contains bits to set clear for EL0 to EL2 > +Example : %> echo 0x4 > ns_exlevel_viinst > + ; Exclude EL2 NS trace. > + > +File : vinst_pe_cmp_start_stop (rw) > +Trace Registers : VIPCSSCTLR > +Notes : Access PE start stop comparator input control registers > + > +File : bb_ctrl (rw) > +Trace Registers : BBCTLR > +Notes : Define ranges that Branch Broadcast will operate in. > + Default (0x0) is all addresses. > +Depends : BB enabled. > + > +File : cyc_threshold (rw) > +Trace Registers : CCCTLR > +Notes : Set the threshold for which cycle counts will be emitted. > + Error if attempt to set below minimum defined in IDR3, masked > + to width of valid bits. > +Depends : CC enabled. > + > +File : syncfreq (rw) > +Trace Registers : SYNCPR > +Notes : Set trace synchronisation period. Power of 2 value, 0 (off) > + or 8-20. Driver defaults to 12 (every 4096 bytes). > + > +File : cntr_idx (rw) > +Trace Registers : none > +Notes : Select the counter to access > +Syntax : 'echo idx > cntr_idx' > + Where idx < nr_cntr > + > +File : cntr_ctrl (rw) > +Trace Registers : CNTCTLR[idx] > +Notes : Set counter control value > +Depends : cntr_idx > +Syntax : 'echo val > cntr_ctrl' > + Where val is per ETMv4 spec. > + > +File : cntrldvr (rw) > +Trace Registers : CNTRLDVR[idx] > +Notes : Set counter reload value > +Depends : cntr_idx > +Syntax : 'echo val > cntrldvr' > + Where val is per ETMv4 spec. > + > +File : nr_cntr (ro) > +Trace Registers : From IDR5 > +Notes : Number of counters implemented. > + > +File : ctxid_idx (rw) > +Trace Registers : None > +Notes : Select the context ID comparator to access > +Syntax : 'echo idx > ctxid_idx' > + Where idx < numcidc > + > +File : ctxid_pid (rw) > +Trace Registers : CIDCVR[idx] > +Notes : Set the context ID comparator value > +Depends : ctxid_idx > + > +File : ctxid_masks (rw) > +Trace Registers : CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7> > +Notes : Pair of values to set the byte masks for 1-8 context ID > + comparators. Automatically clears masked bytes to 0 in CID > + value registers. > +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > ctxid_masks' > + 32 bit values made up of mask bytes, where mN represents a > + byte mask value for Ctxt ID comparator N. > + Second value not required on systems that have fewer than 4 > + context ID comparators > + > +File : numcidc (ro) > +Trace Registers : From IDR4 > +Notes : Number of Context ID comparators > + > +File : vmid_idx (rw) > +Trace Registers : None > +Notes : Select the VM ID comparator to access. > +Syntax : 'echo idx > vmid_idx' > + Where idx < numvmidc > + > +File : vmid_val (rw) > +Trace Registers : VMIDCVR[idx] > +Notes : Set the VM ID comparator value > +Depends : vmid_idx > + > +File : vmid_masks (rw) > +Trace Registers : VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7> > +Notes : Pair of values to set the byte masks for 1-8 VM ID > + comparators. Automatically clears masked bytes to 0 in VMID > + value registers. > +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > vmid_masks' > + Where mN represents a byte mask value for VMID comparator N. > + Second value not required on systems that have fewer than > + 4 VMID comparators. > + > +File : numvmidc (ro) > +Trace Registers : From IDR4 > +Notes : Number of VMID comparators > + > +File : res_idx (rw) > +Trace Registers : None. > +Notes : Select the resource selector control to access. Must be 2 or > + higher as selectors 0 and 1 are hardwired. > +Syntax : 'echo idx > res_idx' > + Where 2 <= idx < nr_resource x 2 > + > +File : res_ctrl (rw) > +Trace Registers : RSCTLR[idx] > +Notes : Set resource selector control value. Value per ETMv4 spec. > +Depends : res_idx > +Syntax : 'echo val > res_cntr' > + Where val is per ETMv4 spec. > + > +File : nr_resource (ro) > +Trace Registers : From IDR4 > +Notes : Number of resource selector pairs > + > +File : event (rw) > +Trace Registers : EVENTCTRL0R > +Notes : Set up to 4 implemented event fields. > +Syntax : 'echo ev3ev2ev1ev0 > event' > + Where evN is an 8 bit event field. Up to 4 event fields make up > + the 32bit input value. Number of valid fields implementation > + dependent defined in IDR0. > + > +File : event_instren (rw) > +Trace Registers : EVENTCTRL1R > +Notes : Choose events which insert event packets into trace stream. > +Depends : EVENTCTRL0R > +Syntax : 'echo bitfield > event_instren' > + Where bitfield is up to 4 bits according to number of event > + fields. > + > +File : event_ts (rw) > +Trace Registers : TSCTLR > +Notes : Set the event that will generate timestamp requests. > +Depends : TS activated > +Syntax : 'echo evfield > event_ts' > + Where evfield is an 8 bit event selector. > + > +File : seq_idx (rw) > +Trace Registers : None > +Notes : Sequencer event register select - 0 to 2 > + > + > +File : seq_state (rw) > +Trace Registers : SEQSTR > +Notes : Sequencer current state - 0 to 3. > + > +File : seq_event (rw) > +Trace Registers : SEQEVR[idx] > +Notes : State transition event registers > +Depends : seq_idx > +Syntax : 'echo evBevF > seq_event' > + Where evBevF is a 16 bit value made up of two event selectors, > + evB - back, evF - forwards. > + > +File : seq_reset_event (rw) > +Trace Registers : SEQRSTEVR > +Notes : Sequencer reset event > +Syntax : 'echo evfield > seq_reset_event' > + Where evfield is an 8 bit event selector. > + > +File : nrseqstate (ro) > +Trace Registers : From IDR5 > +Notes : Number of sequencer states (0 or 4) > + > +File : nr_pe_cmp (ro) > +Trace Registers : From IDR4 > +Notes : Number of PE comparator inputs > + > +File : nr_ext_inp (ro) > +Trace Registers : From IDR5 > +Notes : Number of external inputs > + > +File : nr_ss_cmp (ro) > +Trace Registers : From IDR4 > +Notes : Number of Single Shot control registers > + > +Note: When programming any address comparator the driver will tag the > +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag > +is set, then only the values can be changed using the same sysfs file / type > +used to program it. > + > +Thus:- > +% echo 0 > addr_idx ; select address comparator 0 > +% echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0 and 1. > +% echo 0x2000 > addr_start ; this will error as comparator 0 is a > + ; range comparator > +% echo 2 > addr_idx ; select address comparator 2 > +% echo 0x2000 > addr_start ; this is OK as comparator 2 is unused, > +% echo 0x3000 > addr_stop ; this will error as comparator 2 a start > + ; address comparator > +% echo 2 > addr_idx ; select address comparator 3 > +% echo 0x3000 > addr_stop ; this is OK > + > +To remove programming on all the comparators (and all the other hardware) use > +the reset parameter: > + > +% echo 1 > reset > + > +The ‘mode’ sysfs parameter. > +--------------------------- > + > +This is a bitfield selection parameter that sets the overall trace mode for the > +ETM. The table below describes the bits, using the defines from the driver > +source file, along with a description of the feature these represent. Many > +features are optional and therefore dependent on implementation in the > +hardware. > + > +Bit assignements shown below:- > + > +bit (0) : #define ETM_MODE_EXCLUDE > +description : This is the default value for the include / exclude function when > + setting address ranges. Set 1 for exclude range. When the mode > + parameter is set this value is applied to the currently indexed > + address range. > + > +bit (4) : #define ETM_MODE_BB > +description : Set to enable branch broadcast if supported in hardware [IDR0]. > + > +bit (5) : #define ETMv4_MODE_CYCACC > +description : Set to enable cycle accurate trace if supported [IDR0]. > + > +bit (6) : ETMv4_MODE_CTXID > +description : Set to enable context ID tracing if supported in hardware [IDR2]. > + > +bit (7) : ETM_MODE_VMID > +description : Set to enable virtual machine ID tracing if supported [IDR2]. > + > +bit (11) : ETMv4_MODE_TIMESTAMP > +description : Set to enable timestamp generation if supported [IDR0]. > + > +bit (12) : ETM_MODE_RETURNSTACK > +description : Set to enable trace return stack use if supported [IDR0]. > + > +bit (13-14) : ETM_MODE_QELEM(val) > +description : ‘val’ determines level of Q element support enabled if > + implemented by the ETM [IDR0] > + > +bit (19) : ETM_MODE_ATB_TRIGGER > +description : Set to enable the ATBTRIGGER bit in the event control register > + [EVENTCTLR1] if supported [IDR5]. > + > +bit (20) : ETM_MODE_LPOVERRIDE > +description : Set to enable the LPOVERRIDE bit in the event control register > + [EVENTCTLR1], if supported [IDR5]. > + > +bit (21) : ETM_MODE_ISTALL_EN > +description : Set to enable the ISTALL bit in the stall control register > + [STALLCTLR] > + > +bit (23) : ETM_MODE_INSTPRIO > +description : Set to enable the INSTPRIORITY bit in the stall control register > + [STALLCTLR] , if supported [IDR0]. > + > +bit (24) : ETM_MODE_NOOVERFLOW > +description : Set to enable the NOOVERFLOW bit in the stall control register > + [STALLCTLR], if supported [IDR3]. > + > +bit (25) : ETM_MODE_TRACE_RESET > +description : Set to enable the TRCRESET bit in the viewinst control register > + [VICTLR] , if supported [IDR3]. > + > +bit (26) : ETM_MODE_TRACE_ERR > +description : Set to enable the TRCCTRL bit in the viewinst control register > + [VICTLR]. > + > +bit (27) : ETM_MODE_VIEWINST_STARTSTOP > +description : Set the initial state value of the ViewInst start / stop logic > + in the viewinst control register [VICTLR] > + > +bit (30) : ETM_MODE_EXCL_KERN > +description : Set default trace setup to exclude kernel mode trace (see note a) > + > +bit (31) : ETM_MODE_EXCL_USER > +description : Set default trace setup to exclude user space trace (see note a) > + > +Note a) On startup the ETM is programmed to trace the complete address space > +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to > +set EL exclude bits for NS state in either user space (EL0) or kernel space > +(EL1) in the address range comparator. (the default setting excludes all > +secure EL, and NS EL2) > + > +Once the reset parameter has been used, and/or custom programming has been > +implemented - using these bits will result in the EL bits for address > +comparator 0 being set in the same way. > + > +Note b) Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with > +data trace. As A profile data trace is architecturally prohibited in ETMv4, > +these have been omitted here. Possible uses could be where a kernel has > +support for control of R or M profile infrastructure as part of a heterogeneous > +system. > + > +Bits 17, 28-29 are unused. > + > diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight/coresight.txt > similarity index 100% > rename from Documentation/trace/coresight.txt > rename to Documentation/trace/coresight/coresight.txt > diff --git a/MAINTAINERS b/MAINTAINERS > index 783569e3c4b4..777b77fde29b 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1582,8 +1582,7 @@ R: Suzuki K Poulose <suzuki.poulose@arm.com> > L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) > S: Maintained > F: drivers/hwtracing/coresight/* > -F: Documentation/trace/coresight.txt > -F: Documentation/trace/coresight-cpu-debug.txt > +F: Documentation/trace/coresight/* > F: Documentation/devicetree/bindings/arm/coresight.txt > F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt > F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* > -- > 2.17.1 >
On Mon, Aug 19, 2019 at 09:57:20PM +0100, Mike Leach wrote: > Update existing docs for new sysfs API features. > Add new ETMv4 reference document for sysfs programming. > Move coresight documentation to common directory. > I also get the following warnings when adding the patch: $ git am 0008-coresight-etm4x-docs-Additional-documentation-for-ET.patch Applying: coresight: etm4x: docs: Additional documentation for ETM4x. .git/rebase-apply/patch:620: space before tab in indent. bitfield up to 32 bits setting trace features. .git/rebase-apply/patch:950: space before tab in indent. ; range comparator .git/rebase-apply/patch:954: space before tab in indent. ; address comparator .git/rebase-apply/patch:1057: new blank line at EOF. + warning: 4 lines add whitespace errors. > Signed-off-by: Mike Leach <mike.leach@linaro.org> > --- > .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++--- > .../{ => coresight}/coresight-cpu-debug.txt | 0 > .../coresight/coresight-etm4x-reference.txt | 459 ++++++++++++++++++ > .../trace/{ => coresight}/coresight.txt | 0 > MAINTAINERS | 3 +- > 5 files changed, 575 insertions(+), 70 deletions(-) > rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%) > create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt > rename Documentation/trace/{ => coresight}/coresight.txt (100%) > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > index 36258bc1b473..112c50ae9986 100644 > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > @@ -1,4 +1,4 @@ > -What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source > +What: /sys/bus/coresight/devices/etm<N>/enable_source > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > @@ -8,82 +8,82 @@ Description: (RW) Enable/disable tracing on this specific trace entiry. > of coresight components linking the source to the sink is > configured and managed automatically by the coresight framework. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cpu > +What: /sys/bus/coresight/devices/etm<N>/cpu > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) The CPU this tracing entity is associated with. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp > +What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of PE comparator inputs that are > available for tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp > +What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of address comparator pairs that are > available for tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr > +What: /sys/bus/coresight/devices/etm<N>/nr_cntr > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of counters that are available for > tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp > +What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates how many external inputs are implemented. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc > +What: /sys/bus/coresight/devices/etm<N>/numcidc > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of Context ID comparators that are > available for tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc > +What: /sys/bus/coresight/devices/etm<N>/numvmidc > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of VMID comparators that are available > for tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate > +What: /sys/bus/coresight/devices/etm<N>/nrseqstate > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of sequencer states that are > implemented. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource > +What: /sys/bus/coresight/devices/etm<N>/nr_resource > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of resource selection pairs that are > available for tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp > +What: /sys/bus/coresight/devices/etm<N>/nr_ss_cmp > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Indicates the number of single-shot comparator controls that > are available for tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/reset > +What: /sys/bus/coresight/devices/etm<N>/reset > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (W) Cancels all configuration on a trace unit and set it back > to its boot configuration. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mode > +What: /sys/bus/coresight/devices/etm<N>/mode > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > @@ -91,302 +91,349 @@ Description: (RW) Controls various modes supported by this ETM, for example > P0 instruction tracing, branch broadcast, cycle counting and > context ID tracing. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/pe > +What: /sys/bus/coresight/devices/etm<N>/pe > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls which PE to trace. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event > +What: /sys/bus/coresight/devices/etm<N>/event > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren > +What: /sys/bus/coresight/devices/etm<N>/event_instren > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls the behavior of the events in bank 0 to 3. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts > +What: /sys/bus/coresight/devices/etm<N>/event_ts > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls the insertion of global timestamps in the trace > streams. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq > +What: /sys/bus/coresight/devices/etm<N>/syncfreq > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls how often trace synchronization requests occur. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold > +What: /sys/bus/coresight/devices/etm<N>/cyc_threshold > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Sets the threshold value for cycle counting. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl > +What: /sys/bus/coresight/devices/etm<N>/bb_ctrl > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls which regions in the memory map are enabled to > use branch broadcasting. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_vinst > +What: /sys/bus/coresight/devices/etm<N>/event_vinst > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls instruction trace filtering. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst > +What: /sys/bus/coresight/devices/etm<N>/s_exlevel_vinst > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) In Secure state, each bit controls whether instruction > tracing is enabled for the corresponding exception level. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst > +What: /sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) In non-secure state, each bit controls whether instruction > tracing is enabled for the corresponding exception level. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_idx > +What: /sys/bus/coresight/devices/etm<N>/addr_idx > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Select which address comparator or pair (of comparators) to > work with. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype > +What: /sys/bus/coresight/devices/etm<N>/addr_instdatatype > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls what type of comparison the trace unit performs. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_single > +What: /sys/bus/coresight/devices/etm<N>/addr_single > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Used to setup single address comparator values. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_range > +What: /sys/bus/coresight/devices/etm<N>/addr_range > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Used to setup address range comparator values. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_idx > +What: /sys/bus/coresight/devices/etm<N>/seq_idx > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Select which sequensor. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state > +What: /sys/bus/coresight/devices/etm<N>/seq_state > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Use this to set, or read, the sequencer state. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_event > +What: /sys/bus/coresight/devices/etm<N>/seq_event > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Moves the sequencer state to a specific state. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event > +What: /sys/bus/coresight/devices/etm<N>/seq_reset_event > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Moves the sequencer to state 0 when a programmed event > occurs. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx > +What: /sys/bus/coresight/devices/etm<N>/cntr_idx > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Select which counter unit to work with. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr > +What: /sys/bus/coresight/devices/etm<N>/cntrldvr > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) This sets or returns the reload count value of the > specific counter. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_val > +What: /sys/bus/coresight/devices/etm<N>/cntr_val > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) This sets or returns the current count value of the > specific counter. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl > +What: /sys/bus/coresight/devices/etm<N>/cntr_ctrl > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls the operation of the selected counter. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/res_idx > +What: /sys/bus/coresight/devices/etm<N>/res_idx > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Select which resource selection unit to work with. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl > +What: /sys/bus/coresight/devices/etm<N>/res_ctrl > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Controls the selection of the resources in the trace unit. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx > +What: /sys/bus/coresight/devices/etm<N>/ctxid_idx > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Select which context ID comparator to work with. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid > +What: /sys/bus/coresight/devices/etm<N>/ctxid_pid > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Get/Set the context ID comparator value to trigger on. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks > +What: /sys/bus/coresight/devices/etm<N>/ctxid_masks > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Mask for all 8 context ID comparator value > registers (if implemented). > > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx > +What: /sys/bus/coresight/devices/etm<N>/vmid_idx > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Select which virtual machine ID comparator to work with. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_val > +What: /sys/bus/coresight/devices/etm<N>/vmid_val > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Get/Set the virtual machine ID comparator value to > trigger on. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks > +What: /sys/bus/coresight/devices/etm<N>/vmid_masks > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (RW) Mask for all 8 virtual machine ID comparator value > registers (if implemented). > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr > +What: /sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (RW) Set the Exception Level matching bits for secure and > + non-secure exception levels. > + > +What: /sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (RW) Access the start stop control register for PE input > + comparators. > + > +What: /sys/bus/coresight/devices/etm<N>/addr_cmp_view > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (R) Print the current settings for the selected address > + comparator. > + > +What: /sys/bus/coresight/devices/etm<N>/sshot_idx > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (RW) Select the single shot control register to access. > + > +What: /sys/bus/coresight/devices/etm<N>/sshot_ctrl > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (RW) Access the selected single shot control register. > + > +What: /sys/bus/coresight/devices/etm<N>/sshot_status > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (R) Print the current value of the selected single shot > + status register. > + > +What: /sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl > +Date: August 2019 > +KernelVersion: 5.4 > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > +Description: (RW) Access the selected single show PE comparator control > + register. > + > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the OS Lock Status Register (0x304). > The value it taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Power Down Control Register > (0x310). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Power Down Status Register > (0x314). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trclsr > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the SW Lock Status Register > (0xFB4). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Authentication Status Register > (0xFB8). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevid > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Device ID Register > (0xFC8). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Device Type Register > (0xFCC). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0 > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Peripheral ID0 Register > (0xFE0). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1 > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Peripheral ID1 Register > (0xFE4). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2 > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Peripheral ID2 Register > (0xFE8). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3 > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the Peripheral ID3 Register > (0xFEC). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcconfig > Date: February 2016 > KernelVersion: 4.07 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the trace configuration register > (0x010) as currently set by SW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trctraceid > Date: February 2016 > KernelVersion: 4.07 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Print the content of the trace ID register (0x040). > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr0 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). > The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr1 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). > The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr2 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > @@ -394,7 +441,7 @@ Description: (R) Returns the maximum size of the data value, data address, > VMID, context ID and instuction address in the trace unit > (0x1E8). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr3 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > @@ -403,42 +450,42 @@ Description: (R) Returns the value associated with various resources > architecture specification for more details (0x1E8). > The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr4 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns how many resources the trace unit supports (0x1F0). > The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr5 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns how many resources the trace unit supports (0x1F4). > The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr8 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns the maximum speculation depth of the instruction > trace stream. (0x180). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr9 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns the number of P0 right-hand keys that the trace unit > can use (0x184). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr10 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > Description: (R) Returns the number of P1 right-hand keys that the trace unit > can use (0x188). The value is taken directly from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr11 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > @@ -446,7 +493,7 @@ Description: (R) Returns the number of special P1 right-hand keys that the > trace unit can use (0x18C). The value is taken directly from > the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr12 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > @@ -454,7 +501,7 @@ Description: (R) Returns the number of conditional P1 right-hand keys that > the trace unit can use (0x190). The value is taken directly > from the HW. > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13 > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr13 > Date: April 2015 > KernelVersion: 4.01 > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight/coresight-cpu-debug.txt > similarity index 100% > rename from Documentation/trace/coresight-cpu-debug.txt > rename to Documentation/trace/coresight/coresight-cpu-debug.txt > diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.txt b/Documentation/trace/coresight/coresight-etm4x-reference.txt > new file mode 100644 > index 000000000000..72e81bbbef43 > --- /dev/null > +++ b/Documentation/trace/coresight/coresight-etm4x-reference.txt > @@ -0,0 +1,459 @@ > +ETMv4 sysfs linux driver programming reference - v2. > +==================================================== > + > +Supplement to existing ETMv4 driver documentation. > + > +Sysfs files and directories > +--------------------------- > + > +Root: /sys/bus/coresight/devices/etm<N> > + > + > +The following paragraphs explain the association between sysfs files and the > +ETMv4 registers that they effect. Note the register names are given without > +the ‘TRC’ prefix. > + > +File : mode (rw) > +Trace Registers : {CONFIGR + others} > +Notes : Bit select trace features. See ‘mode’ section below. Bits > + in this will cause equivalent programming of trace config and > + other registers to enable the features requested. > +Syntax & eg : 'echo bitfield > mode' > + bitfield up to 32 bits setting trace features. > +Example : $> echo 0x > mode > + > +File : reset (wo) > +Trace Registers : All > +Notes : Reset all programming to trace nothing / no logic programmed. > +Syntax : 'echo 1 > reset' > + > +File : enable_source (wo) > +Trace Registers : PRGCTLR, All hardware regs. > +Notes : >0: Programs up the hardware with the current values held in > + the driver and enables trace. > + 0: disable trace hardware. > +Syntax : 'echo 1 > enable_source' > + > +File : cpu (ro) > +Trace Registers : None. > +Notes : CPU ID that this ETM is attached to. > +Example :$> cat cpu > + $> 0 > + > +File : addr_idx (rw) > +Trace Registers : None. > +Notes : Virtual register to index address comparator and range > + features. Set index for first of the pair in a range. > +Syntax : 'echo idx > addr_idx' > + Where idx < nr_addr_cmp x 2 > + > +File : addr_range (rw) > +Trace Registers : ACVR[idx, idx+1], VIIECTLR > +Notes : Pair of addresses for a range selected by addr_idx. Include > + / exclude according to the optional parameter, or if omitted > + uses the current ‘mode’ setting. Select comparator range in > + control register. Error if index is odd value. > +Depends : mode, addr_idx > +Syntax : 'echo addr1 addr2 [exclude] > addr_range' > + Where addr1 and addr2 define the range and addr1 < addr2. > + Optional exclude value - 0 for include, 1 for exclude. > +Example : $> echo 0x0000 0x2000 0 > addr_range > + > +File : addr_single (rw) > +Trace Registers : ACVR[idx] > +Notes : Set a single address comparator according to addr_idx. This > + is used if the address comparator is used as part of event > + generation logic etc. > +Depends : addr_idx > +Syntax : 'echo addr1 > addr_single' > + > +File : addr_start (rw) > +Trace Registers : ACVR[idx], VISSCTLR > +Notes : Set a trace start address comparator according to addr_idx. > + Select comparator in control register. > +Depends : addr_idx > +Syntax : 'echo addr1 > addr_start' > + > +File : addr_stop (rw) > +Trace Registers : ACVR[idx], VISSCTLR > +Notes : Set a trace stop address comparator according to addr_idx. > + Select comparator in control register. > +Depends : addr_idx > +Syntax : 'echo addr1 > addr_stop' > + > +File : addr_context (rw) > +Trace Registers : ACATR[idx,{6:4}] > +Notes : Link context ID comparator to address comparator addr_idx > +Depends : addr_idx. > +Syntax : 'echo ctxt_idx > addr_context' > + Where ctxt_idx is the index of the linked context id / vmid > + comparator. > + > +File : addr_ctxtype (rw) > +Trace Registers : ACATR[idx,{3:2}] > +Notes : Input value string. Set type for linked context ID comparator > +Depends : addr_idx > +Syntax : 'echo type > addr_ctxtype' > + Type one of {all, vmid, ctxid, none} > +Example : $> echo ctxid > addr_ctxtype > + > +File : addr_exlevel_s_ns (rw) > +Trace Registers : ACATR[idx,{14:8}] > +Notes : Set the ELx secure and non-secure matching bits for the > + selected address comparator > +Depends : addr_idx > +Syntax : 'echo val > addr_exlevel_s_ns' > + val is a 7 bit value for exception levels to exclude. Input > + value shifted to correct bits in register. > +Example : $> echo 0x4F > addr_exlevel_s_ns > + > +File : addr_instdatatype (rw) > +Trace Registers : ACATR[idx,{1:0}] > +Notes : Set the comparator address type for matching. Driver only > + supports setting instruction address type. > +Depends : addr_idx > + > +File : addr_cmp_view (ro) > +Trace Registers : ACVR[idx, idx+1], ACATR[idx], VIIECTLR > +Notes : Read the currently selected address comparator. If part of > + address range then display both addresses. > +Depends : addr_idx > +Syntax : 'cat addr_cmp_view' > +Example : $> cat addr_cmp_view > + addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00) > + > +File : nr_addr_cmp (ro) > +Trace Registers : From IDR4 > +Notes : Number of address comparator pairs > + > +File : sshot_idx (rw) > +Trace Registers : None > +Notes : Select single shot register set. > + > +File : sshot_ctrl (rw) > +Trace Registers : SSCCR[idx] > +Notes : Access a single shot comparator control register. > +Depends : sshot_idx > +Syntax : 'echo val > sshot_ctrl' > + Writes val into the selected control register. > + > +File : sshot_status (ro) > +Trace Registers : SSCSR[idx] > +Notes : Read a single shot comparator status register > +Depends : sshot_idx > +Syntax : 'cat sshot_status' > + Read status. > +Example : $> cat sshot_status > + 0x1 > + > +File : sshot_pe_ctrl (rw) > +Trace Registers : SSPCICR[idx] > +Notes : Access a single shot PE comparator input control register. > +Depends : sshot_idx > +Syntax : echo val > sshot_pe_ctrl > + Writes val into the selected control register. > + > +File : ns_exlevel_vinst (rw) > +Trace Registers : VICTLR{23:20} > +Notes : Program non-secure exception level filters. Set / clear NS > + exception filter bits. Setting ‘1’ excludes trace from the > + exception level. > +Syntax : 'echo bitfield > ns_exlevel_viinst' > + Where bitfield contains bits to set clear for EL0 to EL2 > +Example : %> echo 0x4 > ns_exlevel_viinst > + ; Exclude EL2 NS trace. > + > +File : vinst_pe_cmp_start_stop (rw) > +Trace Registers : VIPCSSCTLR > +Notes : Access PE start stop comparator input control registers > + > +File : bb_ctrl (rw) > +Trace Registers : BBCTLR > +Notes : Define ranges that Branch Broadcast will operate in. > + Default (0x0) is all addresses. > +Depends : BB enabled. > + > +File : cyc_threshold (rw) > +Trace Registers : CCCTLR > +Notes : Set the threshold for which cycle counts will be emitted. > + Error if attempt to set below minimum defined in IDR3, masked > + to width of valid bits. > +Depends : CC enabled. > + > +File : syncfreq (rw) > +Trace Registers : SYNCPR > +Notes : Set trace synchronisation period. Power of 2 value, 0 (off) > + or 8-20. Driver defaults to 12 (every 4096 bytes). > + > +File : cntr_idx (rw) > +Trace Registers : none > +Notes : Select the counter to access > +Syntax : 'echo idx > cntr_idx' > + Where idx < nr_cntr > + > +File : cntr_ctrl (rw) > +Trace Registers : CNTCTLR[idx] > +Notes : Set counter control value > +Depends : cntr_idx > +Syntax : 'echo val > cntr_ctrl' > + Where val is per ETMv4 spec. > + > +File : cntrldvr (rw) > +Trace Registers : CNTRLDVR[idx] > +Notes : Set counter reload value > +Depends : cntr_idx > +Syntax : 'echo val > cntrldvr' > + Where val is per ETMv4 spec. > + > +File : nr_cntr (ro) > +Trace Registers : From IDR5 > +Notes : Number of counters implemented. > + > +File : ctxid_idx (rw) > +Trace Registers : None > +Notes : Select the context ID comparator to access > +Syntax : 'echo idx > ctxid_idx' > + Where idx < numcidc > + > +File : ctxid_pid (rw) > +Trace Registers : CIDCVR[idx] > +Notes : Set the context ID comparator value > +Depends : ctxid_idx > + > +File : ctxid_masks (rw) > +Trace Registers : CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7> > +Notes : Pair of values to set the byte masks for 1-8 context ID > + comparators. Automatically clears masked bytes to 0 in CID > + value registers. > +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > ctxid_masks' > + 32 bit values made up of mask bytes, where mN represents a > + byte mask value for Ctxt ID comparator N. > + Second value not required on systems that have fewer than 4 > + context ID comparators > + > +File : numcidc (ro) > +Trace Registers : From IDR4 > +Notes : Number of Context ID comparators > + > +File : vmid_idx (rw) > +Trace Registers : None > +Notes : Select the VM ID comparator to access. > +Syntax : 'echo idx > vmid_idx' > + Where idx < numvmidc > + > +File : vmid_val (rw) > +Trace Registers : VMIDCVR[idx] > +Notes : Set the VM ID comparator value > +Depends : vmid_idx > + > +File : vmid_masks (rw) > +Trace Registers : VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7> > +Notes : Pair of values to set the byte masks for 1-8 VM ID > + comparators. Automatically clears masked bytes to 0 in VMID > + value registers. > +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > vmid_masks' > + Where mN represents a byte mask value for VMID comparator N. > + Second value not required on systems that have fewer than > + 4 VMID comparators. > + > +File : numvmidc (ro) > +Trace Registers : From IDR4 > +Notes : Number of VMID comparators > + > +File : res_idx (rw) > +Trace Registers : None. > +Notes : Select the resource selector control to access. Must be 2 or > + higher as selectors 0 and 1 are hardwired. > +Syntax : 'echo idx > res_idx' > + Where 2 <= idx < nr_resource x 2 > + > +File : res_ctrl (rw) > +Trace Registers : RSCTLR[idx] > +Notes : Set resource selector control value. Value per ETMv4 spec. > +Depends : res_idx > +Syntax : 'echo val > res_cntr' > + Where val is per ETMv4 spec. > + > +File : nr_resource (ro) > +Trace Registers : From IDR4 > +Notes : Number of resource selector pairs > + > +File : event (rw) > +Trace Registers : EVENTCTRL0R > +Notes : Set up to 4 implemented event fields. > +Syntax : 'echo ev3ev2ev1ev0 > event' > + Where evN is an 8 bit event field. Up to 4 event fields make up > + the 32bit input value. Number of valid fields implementation > + dependent defined in IDR0. > + > +File : event_instren (rw) > +Trace Registers : EVENTCTRL1R > +Notes : Choose events which insert event packets into trace stream. > +Depends : EVENTCTRL0R > +Syntax : 'echo bitfield > event_instren' > + Where bitfield is up to 4 bits according to number of event > + fields. > + > +File : event_ts (rw) > +Trace Registers : TSCTLR > +Notes : Set the event that will generate timestamp requests. > +Depends : TS activated > +Syntax : 'echo evfield > event_ts' > + Where evfield is an 8 bit event selector. > + > +File : seq_idx (rw) > +Trace Registers : None > +Notes : Sequencer event register select - 0 to 2 > + > + > +File : seq_state (rw) > +Trace Registers : SEQSTR > +Notes : Sequencer current state - 0 to 3. > + > +File : seq_event (rw) > +Trace Registers : SEQEVR[idx] > +Notes : State transition event registers > +Depends : seq_idx > +Syntax : 'echo evBevF > seq_event' > + Where evBevF is a 16 bit value made up of two event selectors, > + evB - back, evF - forwards. > + > +File : seq_reset_event (rw) > +Trace Registers : SEQRSTEVR > +Notes : Sequencer reset event > +Syntax : 'echo evfield > seq_reset_event' > + Where evfield is an 8 bit event selector. > + > +File : nrseqstate (ro) > +Trace Registers : From IDR5 > +Notes : Number of sequencer states (0 or 4) > + > +File : nr_pe_cmp (ro) > +Trace Registers : From IDR4 > +Notes : Number of PE comparator inputs > + > +File : nr_ext_inp (ro) > +Trace Registers : From IDR5 > +Notes : Number of external inputs > + > +File : nr_ss_cmp (ro) > +Trace Registers : From IDR4 > +Notes : Number of Single Shot control registers > + > +Note: When programming any address comparator the driver will tag the > +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag > +is set, then only the values can be changed using the same sysfs file / type > +used to program it. > + > +Thus:- > +% echo 0 > addr_idx ; select address comparator 0 > +% echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0 and 1. > +% echo 0x2000 > addr_start ; this will error as comparator 0 is a > + ; range comparator > +% echo 2 > addr_idx ; select address comparator 2 > +% echo 0x2000 > addr_start ; this is OK as comparator 2 is unused, > +% echo 0x3000 > addr_stop ; this will error as comparator 2 a start > + ; address comparator > +% echo 2 > addr_idx ; select address comparator 3 > +% echo 0x3000 > addr_stop ; this is OK > + > +To remove programming on all the comparators (and all the other hardware) use > +the reset parameter: > + > +% echo 1 > reset > + > +The ‘mode’ sysfs parameter. > +--------------------------- > + > +This is a bitfield selection parameter that sets the overall trace mode for the > +ETM. The table below describes the bits, using the defines from the driver > +source file, along with a description of the feature these represent. Many > +features are optional and therefore dependent on implementation in the > +hardware. > + > +Bit assignements shown below:- > + > +bit (0) : #define ETM_MODE_EXCLUDE > +description : This is the default value for the include / exclude function when > + setting address ranges. Set 1 for exclude range. When the mode > + parameter is set this value is applied to the currently indexed > + address range. > + > +bit (4) : #define ETM_MODE_BB > +description : Set to enable branch broadcast if supported in hardware [IDR0]. > + > +bit (5) : #define ETMv4_MODE_CYCACC > +description : Set to enable cycle accurate trace if supported [IDR0]. > + > +bit (6) : ETMv4_MODE_CTXID > +description : Set to enable context ID tracing if supported in hardware [IDR2]. > + > +bit (7) : ETM_MODE_VMID > +description : Set to enable virtual machine ID tracing if supported [IDR2]. > + > +bit (11) : ETMv4_MODE_TIMESTAMP > +description : Set to enable timestamp generation if supported [IDR0]. > + > +bit (12) : ETM_MODE_RETURNSTACK > +description : Set to enable trace return stack use if supported [IDR0]. > + > +bit (13-14) : ETM_MODE_QELEM(val) > +description : ‘val’ determines level of Q element support enabled if > + implemented by the ETM [IDR0] > + > +bit (19) : ETM_MODE_ATB_TRIGGER > +description : Set to enable the ATBTRIGGER bit in the event control register > + [EVENTCTLR1] if supported [IDR5]. > + > +bit (20) : ETM_MODE_LPOVERRIDE > +description : Set to enable the LPOVERRIDE bit in the event control register > + [EVENTCTLR1], if supported [IDR5]. > + > +bit (21) : ETM_MODE_ISTALL_EN > +description : Set to enable the ISTALL bit in the stall control register > + [STALLCTLR] > + > +bit (23) : ETM_MODE_INSTPRIO > +description : Set to enable the INSTPRIORITY bit in the stall control register > + [STALLCTLR] , if supported [IDR0]. > + > +bit (24) : ETM_MODE_NOOVERFLOW > +description : Set to enable the NOOVERFLOW bit in the stall control register > + [STALLCTLR], if supported [IDR3]. > + > +bit (25) : ETM_MODE_TRACE_RESET > +description : Set to enable the TRCRESET bit in the viewinst control register > + [VICTLR] , if supported [IDR3]. > + > +bit (26) : ETM_MODE_TRACE_ERR > +description : Set to enable the TRCCTRL bit in the viewinst control register > + [VICTLR]. > + > +bit (27) : ETM_MODE_VIEWINST_STARTSTOP > +description : Set the initial state value of the ViewInst start / stop logic > + in the viewinst control register [VICTLR] > + > +bit (30) : ETM_MODE_EXCL_KERN > +description : Set default trace setup to exclude kernel mode trace (see note a) > + > +bit (31) : ETM_MODE_EXCL_USER > +description : Set default trace setup to exclude user space trace (see note a) > + > +Note a) On startup the ETM is programmed to trace the complete address space > +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to > +set EL exclude bits for NS state in either user space (EL0) or kernel space > +(EL1) in the address range comparator. (the default setting excludes all > +secure EL, and NS EL2) > + > +Once the reset parameter has been used, and/or custom programming has been > +implemented - using these bits will result in the EL bits for address > +comparator 0 being set in the same way. > + > +Note b) Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with > +data trace. As A profile data trace is architecturally prohibited in ETMv4, > +these have been omitted here. Possible uses could be where a kernel has > +support for control of R or M profile infrastructure as part of a heterogeneous > +system. > + > +Bits 17, 28-29 are unused. > + > diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight/coresight.txt > similarity index 100% > rename from Documentation/trace/coresight.txt > rename to Documentation/trace/coresight/coresight.txt > diff --git a/MAINTAINERS b/MAINTAINERS > index 783569e3c4b4..777b77fde29b 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -1582,8 +1582,7 @@ R: Suzuki K Poulose <suzuki.poulose@arm.com> > L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) > S: Maintained > F: drivers/hwtracing/coresight/* > -F: Documentation/trace/coresight.txt > -F: Documentation/trace/coresight-cpu-debug.txt > +F: Documentation/trace/coresight/* > F: Documentation/devicetree/bindings/arm/coresight.txt > F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt > F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* > -- > 2.17.1 >
Hi Mathieu, I assume you want the split to be ? :- 1. the update in Documentation/ARM/testing/sysfs-bus-coresight-devices-etm4x 2. the moving of coresight docs to their new common directory. 3. the addition of the new etm4x doc On Tue, 27 Aug 2019 at 23:34, Mathieu Poirier <mathieu.poirier@linaro.org> wrote: > > On Mon, Aug 19, 2019 at 09:57:20PM +0100, Mike Leach wrote: > > Update existing docs for new sysfs API features. > > Add new ETMv4 reference document for sysfs programming. > > Move coresight documentation to common directory. > > > > I also get the following warnings when adding the patch: > > $ git am 0008-coresight-etm4x-docs-Additional-documentation-for-ET.patch > Applying: coresight: etm4x: docs: Additional documentation for ETM4x. > .git/rebase-apply/patch:620: space before tab in indent. > bitfield up to 32 bits setting trace features. > .git/rebase-apply/patch:950: space before tab in indent. > ; range comparator > .git/rebase-apply/patch:954: space before tab in indent. > ; address comparator > .git/rebase-apply/patch:1057: new blank line at EOF. > + > warning: 4 lines add whitespace errors. > OK - I'll re-look at this, but don't recall seeing any errors myself & al cleared by checkpatch. Regards Mike > > Signed-off-by: Mike Leach <mike.leach@linaro.org> > > --- > > .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++--- > > .../{ => coresight}/coresight-cpu-debug.txt | 0 > > .../coresight/coresight-etm4x-reference.txt | 459 ++++++++++++++++++ > > .../trace/{ => coresight}/coresight.txt | 0 > > MAINTAINERS | 3 +- > > 5 files changed, 575 insertions(+), 70 deletions(-) > > rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%) > > create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt > > rename Documentation/trace/{ => coresight}/coresight.txt (100%) > > > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > > index 36258bc1b473..112c50ae9986 100644 > > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > > @@ -1,4 +1,4 @@ > > -What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source > > +What: /sys/bus/coresight/devices/etm<N>/enable_source > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > @@ -8,82 +8,82 @@ Description: (RW) Enable/disable tracing on this specific trace entiry. > > of coresight components linking the source to the sink is > > configured and managed automatically by the coresight framework. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cpu > > +What: /sys/bus/coresight/devices/etm<N>/cpu > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) The CPU this tracing entity is associated with. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp > > +What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Indicates the number of PE comparator inputs that are > > available for tracing. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp > > +What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Indicates the number of address comparator pairs that are > > available for tracing. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr > > +What: /sys/bus/coresight/devices/etm<N>/nr_cntr > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Indicates the number of counters that are available for > > tracing. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp > > +What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Indicates how many external inputs are implemented. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc > > +What: /sys/bus/coresight/devices/etm<N>/numcidc > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Indicates the number of Context ID comparators that are > > available for tracing. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc > > +What: /sys/bus/coresight/devices/etm<N>/numvmidc > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Indicates the number of VMID comparators that are available > > for tracing. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate > > +What: /sys/bus/coresight/devices/etm<N>/nrseqstate > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Indicates the number of sequencer states that are > > implemented. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource > > +What: /sys/bus/coresight/devices/etm<N>/nr_resource > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Indicates the number of resource selection pairs that are > > available for tracing. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp > > +What: /sys/bus/coresight/devices/etm<N>/nr_ss_cmp > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Indicates the number of single-shot comparator controls that > > are available for tracing. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/reset > > +What: /sys/bus/coresight/devices/etm<N>/reset > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (W) Cancels all configuration on a trace unit and set it back > > to its boot configuration. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mode > > +What: /sys/bus/coresight/devices/etm<N>/mode > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > @@ -91,302 +91,349 @@ Description: (RW) Controls various modes supported by this ETM, for example > > P0 instruction tracing, branch broadcast, cycle counting and > > context ID tracing. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/pe > > +What: /sys/bus/coresight/devices/etm<N>/pe > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Controls which PE to trace. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event > > +What: /sys/bus/coresight/devices/etm<N>/event > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren > > +What: /sys/bus/coresight/devices/etm<N>/event_instren > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Controls the behavior of the events in bank 0 to 3. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts > > +What: /sys/bus/coresight/devices/etm<N>/event_ts > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Controls the insertion of global timestamps in the trace > > streams. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq > > +What: /sys/bus/coresight/devices/etm<N>/syncfreq > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Controls how often trace synchronization requests occur. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold > > +What: /sys/bus/coresight/devices/etm<N>/cyc_threshold > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Sets the threshold value for cycle counting. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl > > +What: /sys/bus/coresight/devices/etm<N>/bb_ctrl > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Controls which regions in the memory map are enabled to > > use branch broadcasting. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_vinst > > +What: /sys/bus/coresight/devices/etm<N>/event_vinst > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Controls instruction trace filtering. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst > > +What: /sys/bus/coresight/devices/etm<N>/s_exlevel_vinst > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) In Secure state, each bit controls whether instruction > > tracing is enabled for the corresponding exception level. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst > > +What: /sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) In non-secure state, each bit controls whether instruction > > tracing is enabled for the corresponding exception level. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_idx > > +What: /sys/bus/coresight/devices/etm<N>/addr_idx > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Select which address comparator or pair (of comparators) to > > work with. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype > > +What: /sys/bus/coresight/devices/etm<N>/addr_instdatatype > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Controls what type of comparison the trace unit performs. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_single > > +What: /sys/bus/coresight/devices/etm<N>/addr_single > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Used to setup single address comparator values. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_range > > +What: /sys/bus/coresight/devices/etm<N>/addr_range > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Used to setup address range comparator values. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_idx > > +What: /sys/bus/coresight/devices/etm<N>/seq_idx > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Select which sequensor. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state > > +What: /sys/bus/coresight/devices/etm<N>/seq_state > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Use this to set, or read, the sequencer state. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_event > > +What: /sys/bus/coresight/devices/etm<N>/seq_event > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Moves the sequencer state to a specific state. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event > > +What: /sys/bus/coresight/devices/etm<N>/seq_reset_event > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Moves the sequencer to state 0 when a programmed event > > occurs. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx > > +What: /sys/bus/coresight/devices/etm<N>/cntr_idx > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Select which counter unit to work with. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr > > +What: /sys/bus/coresight/devices/etm<N>/cntrldvr > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) This sets or returns the reload count value of the > > specific counter. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_val > > +What: /sys/bus/coresight/devices/etm<N>/cntr_val > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) This sets or returns the current count value of the > > specific counter. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl > > +What: /sys/bus/coresight/devices/etm<N>/cntr_ctrl > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Controls the operation of the selected counter. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/res_idx > > +What: /sys/bus/coresight/devices/etm<N>/res_idx > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Select which resource selection unit to work with. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl > > +What: /sys/bus/coresight/devices/etm<N>/res_ctrl > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Controls the selection of the resources in the trace unit. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx > > +What: /sys/bus/coresight/devices/etm<N>/ctxid_idx > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Select which context ID comparator to work with. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid > > +What: /sys/bus/coresight/devices/etm<N>/ctxid_pid > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Get/Set the context ID comparator value to trigger on. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks > > +What: /sys/bus/coresight/devices/etm<N>/ctxid_masks > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Mask for all 8 context ID comparator value > > registers (if implemented). > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx > > +What: /sys/bus/coresight/devices/etm<N>/vmid_idx > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Select which virtual machine ID comparator to work with. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_val > > +What: /sys/bus/coresight/devices/etm<N>/vmid_val > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Get/Set the virtual machine ID comparator value to > > trigger on. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks > > +What: /sys/bus/coresight/devices/etm<N>/vmid_masks > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (RW) Mask for all 8 virtual machine ID comparator value > > registers (if implemented). > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr > > +What: /sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns > > +Date: August 2019 > > +KernelVersion: 5.4 > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > +Description: (RW) Set the Exception Level matching bits for secure and > > + non-secure exception levels. > > + > > +What: /sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop > > +Date: August 2019 > > +KernelVersion: 5.4 > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > +Description: (RW) Access the start stop control register for PE input > > + comparators. > > + > > +What: /sys/bus/coresight/devices/etm<N>/addr_cmp_view > > +Date: August 2019 > > +KernelVersion: 5.4 > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > +Description: (R) Print the current settings for the selected address > > + comparator. > > + > > +What: /sys/bus/coresight/devices/etm<N>/sshot_idx > > +Date: August 2019 > > +KernelVersion: 5.4 > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > +Description: (RW) Select the single shot control register to access. > > + > > +What: /sys/bus/coresight/devices/etm<N>/sshot_ctrl > > +Date: August 2019 > > +KernelVersion: 5.4 > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > +Description: (RW) Access the selected single shot control register. > > + > > +What: /sys/bus/coresight/devices/etm<N>/sshot_status > > +Date: August 2019 > > +KernelVersion: 5.4 > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > +Description: (R) Print the current value of the selected single shot > > + status register. > > + > > +What: /sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl > > +Date: August 2019 > > +KernelVersion: 5.4 > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > +Description: (RW) Access the selected single show PE comparator control > > + register. > > + > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the OS Lock Status Register (0x304). > > The value it taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the Power Down Control Register > > (0x310). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the Power Down Status Register > > (0x314). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trclsr > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the SW Lock Status Register > > (0xFB4). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the Authentication Status Register > > (0xFB8). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevid > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the Device ID Register > > (0xFC8). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the Device Type Register > > (0xFCC). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0 > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the Peripheral ID0 Register > > (0xFE0). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1 > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the Peripheral ID1 Register > > (0xFE4). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2 > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the Peripheral ID2 Register > > (0xFE8). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3 > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the Peripheral ID3 Register > > (0xFEC). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcconfig > > Date: February 2016 > > KernelVersion: 4.07 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the trace configuration register > > (0x010) as currently set by SW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trctraceid > > Date: February 2016 > > KernelVersion: 4.07 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Print the content of the trace ID register (0x040). > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0 > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr0 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). > > The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1 > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr1 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). > > The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2 > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr2 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > @@ -394,7 +441,7 @@ Description: (R) Returns the maximum size of the data value, data address, > > VMID, context ID and instuction address in the trace unit > > (0x1E8). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3 > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr3 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > @@ -403,42 +450,42 @@ Description: (R) Returns the value associated with various resources > > architecture specification for more details (0x1E8). > > The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4 > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr4 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Returns how many resources the trace unit supports (0x1F0). > > The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5 > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr5 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Returns how many resources the trace unit supports (0x1F4). > > The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8 > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr8 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Returns the maximum speculation depth of the instruction > > trace stream. (0x180). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9 > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr9 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Returns the number of P0 right-hand keys that the trace unit > > can use (0x184). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10 > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr10 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > Description: (R) Returns the number of P1 right-hand keys that the trace unit > > can use (0x188). The value is taken directly from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11 > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr11 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > @@ -446,7 +493,7 @@ Description: (R) Returns the number of special P1 right-hand keys that the > > trace unit can use (0x18C). The value is taken directly from > > the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12 > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr12 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > @@ -454,7 +501,7 @@ Description: (R) Returns the number of conditional P1 right-hand keys that > > the trace unit can use (0x190). The value is taken directly > > from the HW. > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13 > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr13 > > Date: April 2015 > > KernelVersion: 4.01 > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight/coresight-cpu-debug.txt > > similarity index 100% > > rename from Documentation/trace/coresight-cpu-debug.txt > > rename to Documentation/trace/coresight/coresight-cpu-debug.txt > > diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.txt b/Documentation/trace/coresight/coresight-etm4x-reference.txt > > new file mode 100644 > > index 000000000000..72e81bbbef43 > > --- /dev/null > > +++ b/Documentation/trace/coresight/coresight-etm4x-reference.txt > > @@ -0,0 +1,459 @@ > > +ETMv4 sysfs linux driver programming reference - v2. > > +==================================================== > > + > > +Supplement to existing ETMv4 driver documentation. > > + > > +Sysfs files and directories > > +--------------------------- > > + > > +Root: /sys/bus/coresight/devices/etm<N> > > + > > + > > +The following paragraphs explain the association between sysfs files and the > > +ETMv4 registers that they effect. Note the register names are given without > > +the ‘TRC’ prefix. > > + > > +File : mode (rw) > > +Trace Registers : {CONFIGR + others} > > +Notes : Bit select trace features. See ‘mode’ section below. Bits > > + in this will cause equivalent programming of trace config and > > + other registers to enable the features requested. > > +Syntax & eg : 'echo bitfield > mode' > > + bitfield up to 32 bits setting trace features. > > +Example : $> echo 0x > mode > > + > > +File : reset (wo) > > +Trace Registers : All > > +Notes : Reset all programming to trace nothing / no logic programmed. > > +Syntax : 'echo 1 > reset' > > + > > +File : enable_source (wo) > > +Trace Registers : PRGCTLR, All hardware regs. > > +Notes : >0: Programs up the hardware with the current values held in > > + the driver and enables trace. > > + 0: disable trace hardware. > > +Syntax : 'echo 1 > enable_source' > > + > > +File : cpu (ro) > > +Trace Registers : None. > > +Notes : CPU ID that this ETM is attached to. > > +Example :$> cat cpu > > + $> 0 > > + > > +File : addr_idx (rw) > > +Trace Registers : None. > > +Notes : Virtual register to index address comparator and range > > + features. Set index for first of the pair in a range. > > +Syntax : 'echo idx > addr_idx' > > + Where idx < nr_addr_cmp x 2 > > + > > +File : addr_range (rw) > > +Trace Registers : ACVR[idx, idx+1], VIIECTLR > > +Notes : Pair of addresses for a range selected by addr_idx. Include > > + / exclude according to the optional parameter, or if omitted > > + uses the current ‘mode’ setting. Select comparator range in > > + control register. Error if index is odd value. > > +Depends : mode, addr_idx > > +Syntax : 'echo addr1 addr2 [exclude] > addr_range' > > + Where addr1 and addr2 define the range and addr1 < addr2. > > + Optional exclude value - 0 for include, 1 for exclude. > > +Example : $> echo 0x0000 0x2000 0 > addr_range > > + > > +File : addr_single (rw) > > +Trace Registers : ACVR[idx] > > +Notes : Set a single address comparator according to addr_idx. This > > + is used if the address comparator is used as part of event > > + generation logic etc. > > +Depends : addr_idx > > +Syntax : 'echo addr1 > addr_single' > > + > > +File : addr_start (rw) > > +Trace Registers : ACVR[idx], VISSCTLR > > +Notes : Set a trace start address comparator according to addr_idx. > > + Select comparator in control register. > > +Depends : addr_idx > > +Syntax : 'echo addr1 > addr_start' > > + > > +File : addr_stop (rw) > > +Trace Registers : ACVR[idx], VISSCTLR > > +Notes : Set a trace stop address comparator according to addr_idx. > > + Select comparator in control register. > > +Depends : addr_idx > > +Syntax : 'echo addr1 > addr_stop' > > + > > +File : addr_context (rw) > > +Trace Registers : ACATR[idx,{6:4}] > > +Notes : Link context ID comparator to address comparator addr_idx > > +Depends : addr_idx. > > +Syntax : 'echo ctxt_idx > addr_context' > > + Where ctxt_idx is the index of the linked context id / vmid > > + comparator. > > + > > +File : addr_ctxtype (rw) > > +Trace Registers : ACATR[idx,{3:2}] > > +Notes : Input value string. Set type for linked context ID comparator > > +Depends : addr_idx > > +Syntax : 'echo type > addr_ctxtype' > > + Type one of {all, vmid, ctxid, none} > > +Example : $> echo ctxid > addr_ctxtype > > + > > +File : addr_exlevel_s_ns (rw) > > +Trace Registers : ACATR[idx,{14:8}] > > +Notes : Set the ELx secure and non-secure matching bits for the > > + selected address comparator > > +Depends : addr_idx > > +Syntax : 'echo val > addr_exlevel_s_ns' > > + val is a 7 bit value for exception levels to exclude. Input > > + value shifted to correct bits in register. > > +Example : $> echo 0x4F > addr_exlevel_s_ns > > + > > +File : addr_instdatatype (rw) > > +Trace Registers : ACATR[idx,{1:0}] > > +Notes : Set the comparator address type for matching. Driver only > > + supports setting instruction address type. > > +Depends : addr_idx > > + > > +File : addr_cmp_view (ro) > > +Trace Registers : ACVR[idx, idx+1], ACATR[idx], VIIECTLR > > +Notes : Read the currently selected address comparator. If part of > > + address range then display both addresses. > > +Depends : addr_idx > > +Syntax : 'cat addr_cmp_view' > > +Example : $> cat addr_cmp_view > > + addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00) > > + > > +File : nr_addr_cmp (ro) > > +Trace Registers : From IDR4 > > +Notes : Number of address comparator pairs > > + > > +File : sshot_idx (rw) > > +Trace Registers : None > > +Notes : Select single shot register set. > > + > > +File : sshot_ctrl (rw) > > +Trace Registers : SSCCR[idx] > > +Notes : Access a single shot comparator control register. > > +Depends : sshot_idx > > +Syntax : 'echo val > sshot_ctrl' > > + Writes val into the selected control register. > > + > > +File : sshot_status (ro) > > +Trace Registers : SSCSR[idx] > > +Notes : Read a single shot comparator status register > > +Depends : sshot_idx > > +Syntax : 'cat sshot_status' > > + Read status. > > +Example : $> cat sshot_status > > + 0x1 > > + > > +File : sshot_pe_ctrl (rw) > > +Trace Registers : SSPCICR[idx] > > +Notes : Access a single shot PE comparator input control register. > > +Depends : sshot_idx > > +Syntax : echo val > sshot_pe_ctrl > > + Writes val into the selected control register. > > + > > +File : ns_exlevel_vinst (rw) > > +Trace Registers : VICTLR{23:20} > > +Notes : Program non-secure exception level filters. Set / clear NS > > + exception filter bits. Setting ‘1’ excludes trace from the > > + exception level. > > +Syntax : 'echo bitfield > ns_exlevel_viinst' > > + Where bitfield contains bits to set clear for EL0 to EL2 > > +Example : %> echo 0x4 > ns_exlevel_viinst > > + ; Exclude EL2 NS trace. > > + > > +File : vinst_pe_cmp_start_stop (rw) > > +Trace Registers : VIPCSSCTLR > > +Notes : Access PE start stop comparator input control registers > > + > > +File : bb_ctrl (rw) > > +Trace Registers : BBCTLR > > +Notes : Define ranges that Branch Broadcast will operate in. > > + Default (0x0) is all addresses. > > +Depends : BB enabled. > > + > > +File : cyc_threshold (rw) > > +Trace Registers : CCCTLR > > +Notes : Set the threshold for which cycle counts will be emitted. > > + Error if attempt to set below minimum defined in IDR3, masked > > + to width of valid bits. > > +Depends : CC enabled. > > + > > +File : syncfreq (rw) > > +Trace Registers : SYNCPR > > +Notes : Set trace synchronisation period. Power of 2 value, 0 (off) > > + or 8-20. Driver defaults to 12 (every 4096 bytes). > > + > > +File : cntr_idx (rw) > > +Trace Registers : none > > +Notes : Select the counter to access > > +Syntax : 'echo idx > cntr_idx' > > + Where idx < nr_cntr > > + > > +File : cntr_ctrl (rw) > > +Trace Registers : CNTCTLR[idx] > > +Notes : Set counter control value > > +Depends : cntr_idx > > +Syntax : 'echo val > cntr_ctrl' > > + Where val is per ETMv4 spec. > > + > > +File : cntrldvr (rw) > > +Trace Registers : CNTRLDVR[idx] > > +Notes : Set counter reload value > > +Depends : cntr_idx > > +Syntax : 'echo val > cntrldvr' > > + Where val is per ETMv4 spec. > > + > > +File : nr_cntr (ro) > > +Trace Registers : From IDR5 > > +Notes : Number of counters implemented. > > + > > +File : ctxid_idx (rw) > > +Trace Registers : None > > +Notes : Select the context ID comparator to access > > +Syntax : 'echo idx > ctxid_idx' > > + Where idx < numcidc > > + > > +File : ctxid_pid (rw) > > +Trace Registers : CIDCVR[idx] > > +Notes : Set the context ID comparator value > > +Depends : ctxid_idx > > + > > +File : ctxid_masks (rw) > > +Trace Registers : CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7> > > +Notes : Pair of values to set the byte masks for 1-8 context ID > > + comparators. Automatically clears masked bytes to 0 in CID > > + value registers. > > +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > ctxid_masks' > > + 32 bit values made up of mask bytes, where mN represents a > > + byte mask value for Ctxt ID comparator N. > > + Second value not required on systems that have fewer than 4 > > + context ID comparators > > + > > +File : numcidc (ro) > > +Trace Registers : From IDR4 > > +Notes : Number of Context ID comparators > > + > > +File : vmid_idx (rw) > > +Trace Registers : None > > +Notes : Select the VM ID comparator to access. > > +Syntax : 'echo idx > vmid_idx' > > + Where idx < numvmidc > > + > > +File : vmid_val (rw) > > +Trace Registers : VMIDCVR[idx] > > +Notes : Set the VM ID comparator value > > +Depends : vmid_idx > > + > > +File : vmid_masks (rw) > > +Trace Registers : VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7> > > +Notes : Pair of values to set the byte masks for 1-8 VM ID > > + comparators. Automatically clears masked bytes to 0 in VMID > > + value registers. > > +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > vmid_masks' > > + Where mN represents a byte mask value for VMID comparator N. > > + Second value not required on systems that have fewer than > > + 4 VMID comparators. > > + > > +File : numvmidc (ro) > > +Trace Registers : From IDR4 > > +Notes : Number of VMID comparators > > + > > +File : res_idx (rw) > > +Trace Registers : None. > > +Notes : Select the resource selector control to access. Must be 2 or > > + higher as selectors 0 and 1 are hardwired. > > +Syntax : 'echo idx > res_idx' > > + Where 2 <= idx < nr_resource x 2 > > + > > +File : res_ctrl (rw) > > +Trace Registers : RSCTLR[idx] > > +Notes : Set resource selector control value. Value per ETMv4 spec. > > +Depends : res_idx > > +Syntax : 'echo val > res_cntr' > > + Where val is per ETMv4 spec. > > + > > +File : nr_resource (ro) > > +Trace Registers : From IDR4 > > +Notes : Number of resource selector pairs > > + > > +File : event (rw) > > +Trace Registers : EVENTCTRL0R > > +Notes : Set up to 4 implemented event fields. > > +Syntax : 'echo ev3ev2ev1ev0 > event' > > + Where evN is an 8 bit event field. Up to 4 event fields make up > > + the 32bit input value. Number of valid fields implementation > > + dependent defined in IDR0. > > + > > +File : event_instren (rw) > > +Trace Registers : EVENTCTRL1R > > +Notes : Choose events which insert event packets into trace stream. > > +Depends : EVENTCTRL0R > > +Syntax : 'echo bitfield > event_instren' > > + Where bitfield is up to 4 bits according to number of event > > + fields. > > + > > +File : event_ts (rw) > > +Trace Registers : TSCTLR > > +Notes : Set the event that will generate timestamp requests. > > +Depends : TS activated > > +Syntax : 'echo evfield > event_ts' > > + Where evfield is an 8 bit event selector. > > + > > +File : seq_idx (rw) > > +Trace Registers : None > > +Notes : Sequencer event register select - 0 to 2 > > + > > + > > +File : seq_state (rw) > > +Trace Registers : SEQSTR > > +Notes : Sequencer current state - 0 to 3. > > + > > +File : seq_event (rw) > > +Trace Registers : SEQEVR[idx] > > +Notes : State transition event registers > > +Depends : seq_idx > > +Syntax : 'echo evBevF > seq_event' > > + Where evBevF is a 16 bit value made up of two event selectors, > > + evB - back, evF - forwards. > > + > > +File : seq_reset_event (rw) > > +Trace Registers : SEQRSTEVR > > +Notes : Sequencer reset event > > +Syntax : 'echo evfield > seq_reset_event' > > + Where evfield is an 8 bit event selector. > > + > > +File : nrseqstate (ro) > > +Trace Registers : From IDR5 > > +Notes : Number of sequencer states (0 or 4) > > + > > +File : nr_pe_cmp (ro) > > +Trace Registers : From IDR4 > > +Notes : Number of PE comparator inputs > > + > > +File : nr_ext_inp (ro) > > +Trace Registers : From IDR5 > > +Notes : Number of external inputs > > + > > +File : nr_ss_cmp (ro) > > +Trace Registers : From IDR4 > > +Notes : Number of Single Shot control registers > > + > > +Note: When programming any address comparator the driver will tag the > > +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag > > +is set, then only the values can be changed using the same sysfs file / type > > +used to program it. > > + > > +Thus:- > > +% echo 0 > addr_idx ; select address comparator 0 > > +% echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0 and 1. > > +% echo 0x2000 > addr_start ; this will error as comparator 0 is a > > + ; range comparator > > +% echo 2 > addr_idx ; select address comparator 2 > > +% echo 0x2000 > addr_start ; this is OK as comparator 2 is unused, > > +% echo 0x3000 > addr_stop ; this will error as comparator 2 a start > > + ; address comparator > > +% echo 2 > addr_idx ; select address comparator 3 > > +% echo 0x3000 > addr_stop ; this is OK > > + > > +To remove programming on all the comparators (and all the other hardware) use > > +the reset parameter: > > + > > +% echo 1 > reset > > + > > +The ‘mode’ sysfs parameter. > > +--------------------------- > > + > > +This is a bitfield selection parameter that sets the overall trace mode for the > > +ETM. The table below describes the bits, using the defines from the driver > > +source file, along with a description of the feature these represent. Many > > +features are optional and therefore dependent on implementation in the > > +hardware. > > + > > +Bit assignements shown below:- > > + > > +bit (0) : #define ETM_MODE_EXCLUDE > > +description : This is the default value for the include / exclude function when > > + setting address ranges. Set 1 for exclude range. When the mode > > + parameter is set this value is applied to the currently indexed > > + address range. > > + > > +bit (4) : #define ETM_MODE_BB > > +description : Set to enable branch broadcast if supported in hardware [IDR0]. > > + > > +bit (5) : #define ETMv4_MODE_CYCACC > > +description : Set to enable cycle accurate trace if supported [IDR0]. > > + > > +bit (6) : ETMv4_MODE_CTXID > > +description : Set to enable context ID tracing if supported in hardware [IDR2]. > > + > > +bit (7) : ETM_MODE_VMID > > +description : Set to enable virtual machine ID tracing if supported [IDR2]. > > + > > +bit (11) : ETMv4_MODE_TIMESTAMP > > +description : Set to enable timestamp generation if supported [IDR0]. > > + > > +bit (12) : ETM_MODE_RETURNSTACK > > +description : Set to enable trace return stack use if supported [IDR0]. > > + > > +bit (13-14) : ETM_MODE_QELEM(val) > > +description : ‘val’ determines level of Q element support enabled if > > + implemented by the ETM [IDR0] > > + > > +bit (19) : ETM_MODE_ATB_TRIGGER > > +description : Set to enable the ATBTRIGGER bit in the event control register > > + [EVENTCTLR1] if supported [IDR5]. > > + > > +bit (20) : ETM_MODE_LPOVERRIDE > > +description : Set to enable the LPOVERRIDE bit in the event control register > > + [EVENTCTLR1], if supported [IDR5]. > > + > > +bit (21) : ETM_MODE_ISTALL_EN > > +description : Set to enable the ISTALL bit in the stall control register > > + [STALLCTLR] > > + > > +bit (23) : ETM_MODE_INSTPRIO > > +description : Set to enable the INSTPRIORITY bit in the stall control register > > + [STALLCTLR] , if supported [IDR0]. > > + > > +bit (24) : ETM_MODE_NOOVERFLOW > > +description : Set to enable the NOOVERFLOW bit in the stall control register > > + [STALLCTLR], if supported [IDR3]. > > + > > +bit (25) : ETM_MODE_TRACE_RESET > > +description : Set to enable the TRCRESET bit in the viewinst control register > > + [VICTLR] , if supported [IDR3]. > > + > > +bit (26) : ETM_MODE_TRACE_ERR > > +description : Set to enable the TRCCTRL bit in the viewinst control register > > + [VICTLR]. > > + > > +bit (27) : ETM_MODE_VIEWINST_STARTSTOP > > +description : Set the initial state value of the ViewInst start / stop logic > > + in the viewinst control register [VICTLR] > > + > > +bit (30) : ETM_MODE_EXCL_KERN > > +description : Set default trace setup to exclude kernel mode trace (see note a) > > + > > +bit (31) : ETM_MODE_EXCL_USER > > +description : Set default trace setup to exclude user space trace (see note a) > > + > > +Note a) On startup the ETM is programmed to trace the complete address space > > +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to > > +set EL exclude bits for NS state in either user space (EL0) or kernel space > > +(EL1) in the address range comparator. (the default setting excludes all > > +secure EL, and NS EL2) > > + > > +Once the reset parameter has been used, and/or custom programming has been > > +implemented - using these bits will result in the EL bits for address > > +comparator 0 being set in the same way. > > + > > +Note b) Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with > > +data trace. As A profile data trace is architecturally prohibited in ETMv4, > > +these have been omitted here. Possible uses could be where a kernel has > > +support for control of R or M profile infrastructure as part of a heterogeneous > > +system. > > + > > +Bits 17, 28-29 are unused. > > + > > diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight/coresight.txt > > similarity index 100% > > rename from Documentation/trace/coresight.txt > > rename to Documentation/trace/coresight/coresight.txt > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 783569e3c4b4..777b77fde29b 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -1582,8 +1582,7 @@ R: Suzuki K Poulose <suzuki.poulose@arm.com> > > L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) > > S: Maintained > > F: drivers/hwtracing/coresight/* > > -F: Documentation/trace/coresight.txt > > -F: Documentation/trace/coresight-cpu-debug.txt > > +F: Documentation/trace/coresight/* > > F: Documentation/devicetree/bindings/arm/coresight.txt > > F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt > > F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* > > -- > > 2.17.1 > >
On Wed, 28 Aug 2019 at 08:20, Mike Leach <mike.leach@linaro.org> wrote: > > Hi Mathieu, > > I assume you want the split to be ? :- > 1. the update in Documentation/ARM/testing/sysfs-bus-coresight-devices-etm4x > 2. the moving of coresight docs to their new common directory. > 3. the addition of the new etm4x doc Yes, that would be great. > > On Tue, 27 Aug 2019 at 23:34, Mathieu Poirier > <mathieu.poirier@linaro.org> wrote: > > > > On Mon, Aug 19, 2019 at 09:57:20PM +0100, Mike Leach wrote: > > > Update existing docs for new sysfs API features. > > > Add new ETMv4 reference document for sysfs programming. > > > Move coresight documentation to common directory. > > > > > > > I also get the following warnings when adding the patch: > > > > $ git am 0008-coresight-etm4x-docs-Additional-documentation-for-ET.patch > > Applying: coresight: etm4x: docs: Additional documentation for ETM4x. > > .git/rebase-apply/patch:620: space before tab in indent. > > bitfield up to 32 bits setting trace features. > > .git/rebase-apply/patch:950: space before tab in indent. > > ; range comparator > > .git/rebase-apply/patch:954: space before tab in indent. > > ; address comparator > > .git/rebase-apply/patch:1057: new blank line at EOF. > > + > > warning: 4 lines add whitespace errors. > > > > OK - I'll re-look at this, but don't recall seeing any errors myself > & al cleared by checkpatch. I didn't get any errors from checkpatch either. I got these while applying the patch. > > Regards > > Mike > > > > > Signed-off-by: Mike Leach <mike.leach@linaro.org> > > > --- > > > .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++--- > > > .../{ => coresight}/coresight-cpu-debug.txt | 0 > > > .../coresight/coresight-etm4x-reference.txt | 459 ++++++++++++++++++ > > > .../trace/{ => coresight}/coresight.txt | 0 > > > MAINTAINERS | 3 +- > > > 5 files changed, 575 insertions(+), 70 deletions(-) > > > rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%) > > > create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt > > > rename Documentation/trace/{ => coresight}/coresight.txt (100%) > > > > > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > > > index 36258bc1b473..112c50ae9986 100644 > > > --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > > > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x > > > @@ -1,4 +1,4 @@ > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source > > > +What: /sys/bus/coresight/devices/etm<N>/enable_source > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > @@ -8,82 +8,82 @@ Description: (RW) Enable/disable tracing on this specific trace entiry. > > > of coresight components linking the source to the sink is > > > configured and managed automatically by the coresight framework. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cpu > > > +What: /sys/bus/coresight/devices/etm<N>/cpu > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) The CPU this tracing entity is associated with. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp > > > +What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Indicates the number of PE comparator inputs that are > > > available for tracing. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp > > > +What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Indicates the number of address comparator pairs that are > > > available for tracing. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr > > > +What: /sys/bus/coresight/devices/etm<N>/nr_cntr > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Indicates the number of counters that are available for > > > tracing. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp > > > +What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Indicates how many external inputs are implemented. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc > > > +What: /sys/bus/coresight/devices/etm<N>/numcidc > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Indicates the number of Context ID comparators that are > > > available for tracing. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc > > > +What: /sys/bus/coresight/devices/etm<N>/numvmidc > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Indicates the number of VMID comparators that are available > > > for tracing. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate > > > +What: /sys/bus/coresight/devices/etm<N>/nrseqstate > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Indicates the number of sequencer states that are > > > implemented. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource > > > +What: /sys/bus/coresight/devices/etm<N>/nr_resource > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Indicates the number of resource selection pairs that are > > > available for tracing. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp > > > +What: /sys/bus/coresight/devices/etm<N>/nr_ss_cmp > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Indicates the number of single-shot comparator controls that > > > are available for tracing. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/reset > > > +What: /sys/bus/coresight/devices/etm<N>/reset > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (W) Cancels all configuration on a trace unit and set it back > > > to its boot configuration. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mode > > > +What: /sys/bus/coresight/devices/etm<N>/mode > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > @@ -91,302 +91,349 @@ Description: (RW) Controls various modes supported by this ETM, for example > > > P0 instruction tracing, branch broadcast, cycle counting and > > > context ID tracing. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/pe > > > +What: /sys/bus/coresight/devices/etm<N>/pe > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Controls which PE to trace. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event > > > +What: /sys/bus/coresight/devices/etm<N>/event > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren > > > +What: /sys/bus/coresight/devices/etm<N>/event_instren > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Controls the behavior of the events in bank 0 to 3. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts > > > +What: /sys/bus/coresight/devices/etm<N>/event_ts > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Controls the insertion of global timestamps in the trace > > > streams. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq > > > +What: /sys/bus/coresight/devices/etm<N>/syncfreq > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Controls how often trace synchronization requests occur. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold > > > +What: /sys/bus/coresight/devices/etm<N>/cyc_threshold > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Sets the threshold value for cycle counting. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl > > > +What: /sys/bus/coresight/devices/etm<N>/bb_ctrl > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Controls which regions in the memory map are enabled to > > > use branch broadcasting. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/event_vinst > > > +What: /sys/bus/coresight/devices/etm<N>/event_vinst > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Controls instruction trace filtering. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst > > > +What: /sys/bus/coresight/devices/etm<N>/s_exlevel_vinst > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) In Secure state, each bit controls whether instruction > > > tracing is enabled for the corresponding exception level. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst > > > +What: /sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) In non-secure state, each bit controls whether instruction > > > tracing is enabled for the corresponding exception level. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_idx > > > +What: /sys/bus/coresight/devices/etm<N>/addr_idx > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Select which address comparator or pair (of comparators) to > > > work with. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype > > > +What: /sys/bus/coresight/devices/etm<N>/addr_instdatatype > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Controls what type of comparison the trace unit performs. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_single > > > +What: /sys/bus/coresight/devices/etm<N>/addr_single > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Used to setup single address comparator values. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_range > > > +What: /sys/bus/coresight/devices/etm<N>/addr_range > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Used to setup address range comparator values. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_idx > > > +What: /sys/bus/coresight/devices/etm<N>/seq_idx > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Select which sequensor. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state > > > +What: /sys/bus/coresight/devices/etm<N>/seq_state > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Use this to set, or read, the sequencer state. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_event > > > +What: /sys/bus/coresight/devices/etm<N>/seq_event > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Moves the sequencer state to a specific state. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event > > > +What: /sys/bus/coresight/devices/etm<N>/seq_reset_event > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Moves the sequencer to state 0 when a programmed event > > > occurs. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx > > > +What: /sys/bus/coresight/devices/etm<N>/cntr_idx > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Select which counter unit to work with. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr > > > +What: /sys/bus/coresight/devices/etm<N>/cntrldvr > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) This sets or returns the reload count value of the > > > specific counter. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_val > > > +What: /sys/bus/coresight/devices/etm<N>/cntr_val > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) This sets or returns the current count value of the > > > specific counter. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl > > > +What: /sys/bus/coresight/devices/etm<N>/cntr_ctrl > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Controls the operation of the selected counter. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/res_idx > > > +What: /sys/bus/coresight/devices/etm<N>/res_idx > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Select which resource selection unit to work with. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl > > > +What: /sys/bus/coresight/devices/etm<N>/res_ctrl > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Controls the selection of the resources in the trace unit. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx > > > +What: /sys/bus/coresight/devices/etm<N>/ctxid_idx > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Select which context ID comparator to work with. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid > > > +What: /sys/bus/coresight/devices/etm<N>/ctxid_pid > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Get/Set the context ID comparator value to trigger on. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks > > > +What: /sys/bus/coresight/devices/etm<N>/ctxid_masks > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Mask for all 8 context ID comparator value > > > registers (if implemented). > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx > > > +What: /sys/bus/coresight/devices/etm<N>/vmid_idx > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Select which virtual machine ID comparator to work with. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_val > > > +What: /sys/bus/coresight/devices/etm<N>/vmid_val > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Get/Set the virtual machine ID comparator value to > > > trigger on. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks > > > +What: /sys/bus/coresight/devices/etm<N>/vmid_masks > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (RW) Mask for all 8 virtual machine ID comparator value > > > registers (if implemented). > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr > > > +What: /sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns > > > +Date: August 2019 > > > +KernelVersion: 5.4 > > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > +Description: (RW) Set the Exception Level matching bits for secure and > > > + non-secure exception levels. > > > + > > > +What: /sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop > > > +Date: August 2019 > > > +KernelVersion: 5.4 > > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > +Description: (RW) Access the start stop control register for PE input > > > + comparators. > > > + > > > +What: /sys/bus/coresight/devices/etm<N>/addr_cmp_view > > > +Date: August 2019 > > > +KernelVersion: 5.4 > > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > +Description: (R) Print the current settings for the selected address > > > + comparator. > > > + > > > +What: /sys/bus/coresight/devices/etm<N>/sshot_idx > > > +Date: August 2019 > > > +KernelVersion: 5.4 > > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > +Description: (RW) Select the single shot control register to access. > > > + > > > +What: /sys/bus/coresight/devices/etm<N>/sshot_ctrl > > > +Date: August 2019 > > > +KernelVersion: 5.4 > > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > +Description: (RW) Access the selected single shot control register. > > > + > > > +What: /sys/bus/coresight/devices/etm<N>/sshot_status > > > +Date: August 2019 > > > +KernelVersion: 5.4 > > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > +Description: (R) Print the current value of the selected single shot > > > + status register. > > > + > > > +What: /sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl > > > +Date: August 2019 > > > +KernelVersion: 5.4 > > > +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > +Description: (RW) Access the selected single show PE comparator control > > > + register. > > > + > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the OS Lock Status Register (0x304). > > > The value it taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the Power Down Control Register > > > (0x310). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the Power Down Status Register > > > (0x314). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trclsr > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the SW Lock Status Register > > > (0xFB4). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the Authentication Status Register > > > (0xFB8). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevid > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the Device ID Register > > > (0xFC8). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the Device Type Register > > > (0xFCC). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0 > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the Peripheral ID0 Register > > > (0xFE0). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1 > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the Peripheral ID1 Register > > > (0xFE4). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2 > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the Peripheral ID2 Register > > > (0xFE8). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3 > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the Peripheral ID3 Register > > > (0xFEC). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcconfig > > > Date: February 2016 > > > KernelVersion: 4.07 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the trace configuration register > > > (0x010) as currently set by SW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid > > > +What: /sys/bus/coresight/devices/etm<N>/mgmt/trctraceid > > > Date: February 2016 > > > KernelVersion: 4.07 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Print the content of the trace ID register (0x040). > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0 > > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr0 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). > > > The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1 > > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr1 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). > > > The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2 > > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr2 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > @@ -394,7 +441,7 @@ Description: (R) Returns the maximum size of the data value, data address, > > > VMID, context ID and instuction address in the trace unit > > > (0x1E8). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3 > > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr3 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > @@ -403,42 +450,42 @@ Description: (R) Returns the value associated with various resources > > > architecture specification for more details (0x1E8). > > > The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4 > > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr4 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Returns how many resources the trace unit supports (0x1F0). > > > The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5 > > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr5 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Returns how many resources the trace unit supports (0x1F4). > > > The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8 > > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr8 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Returns the maximum speculation depth of the instruction > > > trace stream. (0x180). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9 > > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr9 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Returns the number of P0 right-hand keys that the trace unit > > > can use (0x184). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10 > > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr10 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > Description: (R) Returns the number of P1 right-hand keys that the trace unit > > > can use (0x188). The value is taken directly from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11 > > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr11 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > @@ -446,7 +493,7 @@ Description: (R) Returns the number of special P1 right-hand keys that the > > > trace unit can use (0x18C). The value is taken directly from > > > the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12 > > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr12 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > @@ -454,7 +501,7 @@ Description: (R) Returns the number of conditional P1 right-hand keys that > > > the trace unit can use (0x190). The value is taken directly > > > from the HW. > > > > > > -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13 > > > +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr13 > > > Date: April 2015 > > > KernelVersion: 4.01 > > > Contact: Mathieu Poirier <mathieu.poirier@linaro.org> > > > diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight/coresight-cpu-debug.txt > > > similarity index 100% > > > rename from Documentation/trace/coresight-cpu-debug.txt > > > rename to Documentation/trace/coresight/coresight-cpu-debug.txt > > > diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.txt b/Documentation/trace/coresight/coresight-etm4x-reference.txt > > > new file mode 100644 > > > index 000000000000..72e81bbbef43 > > > --- /dev/null > > > +++ b/Documentation/trace/coresight/coresight-etm4x-reference.txt > > > @@ -0,0 +1,459 @@ > > > +ETMv4 sysfs linux driver programming reference - v2. > > > +==================================================== > > > + > > > +Supplement to existing ETMv4 driver documentation. > > > + > > > +Sysfs files and directories > > > +--------------------------- > > > + > > > +Root: /sys/bus/coresight/devices/etm<N> > > > + > > > + > > > +The following paragraphs explain the association between sysfs files and the > > > +ETMv4 registers that they effect. Note the register names are given without > > > +the ‘TRC’ prefix. > > > + > > > +File : mode (rw) > > > +Trace Registers : {CONFIGR + others} > > > +Notes : Bit select trace features. See ‘mode’ section below. Bits > > > + in this will cause equivalent programming of trace config and > > > + other registers to enable the features requested. > > > +Syntax & eg : 'echo bitfield > mode' > > > + bitfield up to 32 bits setting trace features. > > > +Example : $> echo 0x > mode > > > + > > > +File : reset (wo) > > > +Trace Registers : All > > > +Notes : Reset all programming to trace nothing / no logic programmed. > > > +Syntax : 'echo 1 > reset' > > > + > > > +File : enable_source (wo) > > > +Trace Registers : PRGCTLR, All hardware regs. > > > +Notes : >0: Programs up the hardware with the current values held in > > > + the driver and enables trace. > > > + 0: disable trace hardware. > > > +Syntax : 'echo 1 > enable_source' > > > + > > > +File : cpu (ro) > > > +Trace Registers : None. > > > +Notes : CPU ID that this ETM is attached to. > > > +Example :$> cat cpu > > > + $> 0 > > > + > > > +File : addr_idx (rw) > > > +Trace Registers : None. > > > +Notes : Virtual register to index address comparator and range > > > + features. Set index for first of the pair in a range. > > > +Syntax : 'echo idx > addr_idx' > > > + Where idx < nr_addr_cmp x 2 > > > + > > > +File : addr_range (rw) > > > +Trace Registers : ACVR[idx, idx+1], VIIECTLR > > > +Notes : Pair of addresses for a range selected by addr_idx. Include > > > + / exclude according to the optional parameter, or if omitted > > > + uses the current ‘mode’ setting. Select comparator range in > > > + control register. Error if index is odd value. > > > +Depends : mode, addr_idx > > > +Syntax : 'echo addr1 addr2 [exclude] > addr_range' > > > + Where addr1 and addr2 define the range and addr1 < addr2. > > > + Optional exclude value - 0 for include, 1 for exclude. > > > +Example : $> echo 0x0000 0x2000 0 > addr_range > > > + > > > +File : addr_single (rw) > > > +Trace Registers : ACVR[idx] > > > +Notes : Set a single address comparator according to addr_idx. This > > > + is used if the address comparator is used as part of event > > > + generation logic etc. > > > +Depends : addr_idx > > > +Syntax : 'echo addr1 > addr_single' > > > + > > > +File : addr_start (rw) > > > +Trace Registers : ACVR[idx], VISSCTLR > > > +Notes : Set a trace start address comparator according to addr_idx. > > > + Select comparator in control register. > > > +Depends : addr_idx > > > +Syntax : 'echo addr1 > addr_start' > > > + > > > +File : addr_stop (rw) > > > +Trace Registers : ACVR[idx], VISSCTLR > > > +Notes : Set a trace stop address comparator according to addr_idx. > > > + Select comparator in control register. > > > +Depends : addr_idx > > > +Syntax : 'echo addr1 > addr_stop' > > > + > > > +File : addr_context (rw) > > > +Trace Registers : ACATR[idx,{6:4}] > > > +Notes : Link context ID comparator to address comparator addr_idx > > > +Depends : addr_idx. > > > +Syntax : 'echo ctxt_idx > addr_context' > > > + Where ctxt_idx is the index of the linked context id / vmid > > > + comparator. > > > + > > > +File : addr_ctxtype (rw) > > > +Trace Registers : ACATR[idx,{3:2}] > > > +Notes : Input value string. Set type for linked context ID comparator > > > +Depends : addr_idx > > > +Syntax : 'echo type > addr_ctxtype' > > > + Type one of {all, vmid, ctxid, none} > > > +Example : $> echo ctxid > addr_ctxtype > > > + > > > +File : addr_exlevel_s_ns (rw) > > > +Trace Registers : ACATR[idx,{14:8}] > > > +Notes : Set the ELx secure and non-secure matching bits for the > > > + selected address comparator > > > +Depends : addr_idx > > > +Syntax : 'echo val > addr_exlevel_s_ns' > > > + val is a 7 bit value for exception levels to exclude. Input > > > + value shifted to correct bits in register. > > > +Example : $> echo 0x4F > addr_exlevel_s_ns > > > + > > > +File : addr_instdatatype (rw) > > > +Trace Registers : ACATR[idx,{1:0}] > > > +Notes : Set the comparator address type for matching. Driver only > > > + supports setting instruction address type. > > > +Depends : addr_idx > > > + > > > +File : addr_cmp_view (ro) > > > +Trace Registers : ACVR[idx, idx+1], ACATR[idx], VIIECTLR > > > +Notes : Read the currently selected address comparator. If part of > > > + address range then display both addresses. > > > +Depends : addr_idx > > > +Syntax : 'cat addr_cmp_view' > > > +Example : $> cat addr_cmp_view > > > + addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00) > > > + > > > +File : nr_addr_cmp (ro) > > > +Trace Registers : From IDR4 > > > +Notes : Number of address comparator pairs > > > + > > > +File : sshot_idx (rw) > > > +Trace Registers : None > > > +Notes : Select single shot register set. > > > + > > > +File : sshot_ctrl (rw) > > > +Trace Registers : SSCCR[idx] > > > +Notes : Access a single shot comparator control register. > > > +Depends : sshot_idx > > > +Syntax : 'echo val > sshot_ctrl' > > > + Writes val into the selected control register. > > > + > > > +File : sshot_status (ro) > > > +Trace Registers : SSCSR[idx] > > > +Notes : Read a single shot comparator status register > > > +Depends : sshot_idx > > > +Syntax : 'cat sshot_status' > > > + Read status. > > > +Example : $> cat sshot_status > > > + 0x1 > > > + > > > +File : sshot_pe_ctrl (rw) > > > +Trace Registers : SSPCICR[idx] > > > +Notes : Access a single shot PE comparator input control register. > > > +Depends : sshot_idx > > > +Syntax : echo val > sshot_pe_ctrl > > > + Writes val into the selected control register. > > > + > > > +File : ns_exlevel_vinst (rw) > > > +Trace Registers : VICTLR{23:20} > > > +Notes : Program non-secure exception level filters. Set / clear NS > > > + exception filter bits. Setting ‘1’ excludes trace from the > > > + exception level. > > > +Syntax : 'echo bitfield > ns_exlevel_viinst' > > > + Where bitfield contains bits to set clear for EL0 to EL2 > > > +Example : %> echo 0x4 > ns_exlevel_viinst > > > + ; Exclude EL2 NS trace. > > > + > > > +File : vinst_pe_cmp_start_stop (rw) > > > +Trace Registers : VIPCSSCTLR > > > +Notes : Access PE start stop comparator input control registers > > > + > > > +File : bb_ctrl (rw) > > > +Trace Registers : BBCTLR > > > +Notes : Define ranges that Branch Broadcast will operate in. > > > + Default (0x0) is all addresses. > > > +Depends : BB enabled. > > > + > > > +File : cyc_threshold (rw) > > > +Trace Registers : CCCTLR > > > +Notes : Set the threshold for which cycle counts will be emitted. > > > + Error if attempt to set below minimum defined in IDR3, masked > > > + to width of valid bits. > > > +Depends : CC enabled. > > > + > > > +File : syncfreq (rw) > > > +Trace Registers : SYNCPR > > > +Notes : Set trace synchronisation period. Power of 2 value, 0 (off) > > > + or 8-20. Driver defaults to 12 (every 4096 bytes). > > > + > > > +File : cntr_idx (rw) > > > +Trace Registers : none > > > +Notes : Select the counter to access > > > +Syntax : 'echo idx > cntr_idx' > > > + Where idx < nr_cntr > > > + > > > +File : cntr_ctrl (rw) > > > +Trace Registers : CNTCTLR[idx] > > > +Notes : Set counter control value > > > +Depends : cntr_idx > > > +Syntax : 'echo val > cntr_ctrl' > > > + Where val is per ETMv4 spec. > > > + > > > +File : cntrldvr (rw) > > > +Trace Registers : CNTRLDVR[idx] > > > +Notes : Set counter reload value > > > +Depends : cntr_idx > > > +Syntax : 'echo val > cntrldvr' > > > + Where val is per ETMv4 spec. > > > + > > > +File : nr_cntr (ro) > > > +Trace Registers : From IDR5 > > > +Notes : Number of counters implemented. > > > + > > > +File : ctxid_idx (rw) > > > +Trace Registers : None > > > +Notes : Select the context ID comparator to access > > > +Syntax : 'echo idx > ctxid_idx' > > > + Where idx < numcidc > > > + > > > +File : ctxid_pid (rw) > > > +Trace Registers : CIDCVR[idx] > > > +Notes : Set the context ID comparator value > > > +Depends : ctxid_idx > > > + > > > +File : ctxid_masks (rw) > > > +Trace Registers : CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7> > > > +Notes : Pair of values to set the byte masks for 1-8 context ID > > > + comparators. Automatically clears masked bytes to 0 in CID > > > + value registers. > > > +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > ctxid_masks' > > > + 32 bit values made up of mask bytes, where mN represents a > > > + byte mask value for Ctxt ID comparator N. > > > + Second value not required on systems that have fewer than 4 > > > + context ID comparators > > > + > > > +File : numcidc (ro) > > > +Trace Registers : From IDR4 > > > +Notes : Number of Context ID comparators > > > + > > > +File : vmid_idx (rw) > > > +Trace Registers : None > > > +Notes : Select the VM ID comparator to access. > > > +Syntax : 'echo idx > vmid_idx' > > > + Where idx < numvmidc > > > + > > > +File : vmid_val (rw) > > > +Trace Registers : VMIDCVR[idx] > > > +Notes : Set the VM ID comparator value > > > +Depends : vmid_idx > > > + > > > +File : vmid_masks (rw) > > > +Trace Registers : VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7> > > > +Notes : Pair of values to set the byte masks for 1-8 VM ID > > > + comparators. Automatically clears masked bytes to 0 in VMID > > > + value registers. > > > +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > vmid_masks' > > > + Where mN represents a byte mask value for VMID comparator N. > > > + Second value not required on systems that have fewer than > > > + 4 VMID comparators. > > > + > > > +File : numvmidc (ro) > > > +Trace Registers : From IDR4 > > > +Notes : Number of VMID comparators > > > + > > > +File : res_idx (rw) > > > +Trace Registers : None. > > > +Notes : Select the resource selector control to access. Must be 2 or > > > + higher as selectors 0 and 1 are hardwired. > > > +Syntax : 'echo idx > res_idx' > > > + Where 2 <= idx < nr_resource x 2 > > > + > > > +File : res_ctrl (rw) > > > +Trace Registers : RSCTLR[idx] > > > +Notes : Set resource selector control value. Value per ETMv4 spec. > > > +Depends : res_idx > > > +Syntax : 'echo val > res_cntr' > > > + Where val is per ETMv4 spec. > > > + > > > +File : nr_resource (ro) > > > +Trace Registers : From IDR4 > > > +Notes : Number of resource selector pairs > > > + > > > +File : event (rw) > > > +Trace Registers : EVENTCTRL0R > > > +Notes : Set up to 4 implemented event fields. > > > +Syntax : 'echo ev3ev2ev1ev0 > event' > > > + Where evN is an 8 bit event field. Up to 4 event fields make up > > > + the 32bit input value. Number of valid fields implementation > > > + dependent defined in IDR0. > > > + > > > +File : event_instren (rw) > > > +Trace Registers : EVENTCTRL1R > > > +Notes : Choose events which insert event packets into trace stream. > > > +Depends : EVENTCTRL0R > > > +Syntax : 'echo bitfield > event_instren' > > > + Where bitfield is up to 4 bits according to number of event > > > + fields. > > > + > > > +File : event_ts (rw) > > > +Trace Registers : TSCTLR > > > +Notes : Set the event that will generate timestamp requests. > > > +Depends : TS activated > > > +Syntax : 'echo evfield > event_ts' > > > + Where evfield is an 8 bit event selector. > > > + > > > +File : seq_idx (rw) > > > +Trace Registers : None > > > +Notes : Sequencer event register select - 0 to 2 > > > + > > > + > > > +File : seq_state (rw) > > > +Trace Registers : SEQSTR > > > +Notes : Sequencer current state - 0 to 3. > > > + > > > +File : seq_event (rw) > > > +Trace Registers : SEQEVR[idx] > > > +Notes : State transition event registers > > > +Depends : seq_idx > > > +Syntax : 'echo evBevF > seq_event' > > > + Where evBevF is a 16 bit value made up of two event selectors, > > > + evB - back, evF - forwards. > > > + > > > +File : seq_reset_event (rw) > > > +Trace Registers : SEQRSTEVR > > > +Notes : Sequencer reset event > > > +Syntax : 'echo evfield > seq_reset_event' > > > + Where evfield is an 8 bit event selector. > > > + > > > +File : nrseqstate (ro) > > > +Trace Registers : From IDR5 > > > +Notes : Number of sequencer states (0 or 4) > > > + > > > +File : nr_pe_cmp (ro) > > > +Trace Registers : From IDR4 > > > +Notes : Number of PE comparator inputs > > > + > > > +File : nr_ext_inp (ro) > > > +Trace Registers : From IDR5 > > > +Notes : Number of external inputs > > > + > > > +File : nr_ss_cmp (ro) > > > +Trace Registers : From IDR4 > > > +Notes : Number of Single Shot control registers > > > + > > > +Note: When programming any address comparator the driver will tag the > > > +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag > > > +is set, then only the values can be changed using the same sysfs file / type > > > +used to program it. > > > + > > > +Thus:- > > > +% echo 0 > addr_idx ; select address comparator 0 > > > +% echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0 and 1. > > > +% echo 0x2000 > addr_start ; this will error as comparator 0 is a > > > + ; range comparator > > > +% echo 2 > addr_idx ; select address comparator 2 > > > +% echo 0x2000 > addr_start ; this is OK as comparator 2 is unused, > > > +% echo 0x3000 > addr_stop ; this will error as comparator 2 a start > > > + ; address comparator > > > +% echo 2 > addr_idx ; select address comparator 3 > > > +% echo 0x3000 > addr_stop ; this is OK > > > + > > > +To remove programming on all the comparators (and all the other hardware) use > > > +the reset parameter: > > > + > > > +% echo 1 > reset > > > + > > > +The ‘mode’ sysfs parameter. > > > +--------------------------- > > > + > > > +This is a bitfield selection parameter that sets the overall trace mode for the > > > +ETM. The table below describes the bits, using the defines from the driver > > > +source file, along with a description of the feature these represent. Many > > > +features are optional and therefore dependent on implementation in the > > > +hardware. > > > + > > > +Bit assignements shown below:- > > > + > > > +bit (0) : #define ETM_MODE_EXCLUDE > > > +description : This is the default value for the include / exclude function when > > > + setting address ranges. Set 1 for exclude range. When the mode > > > + parameter is set this value is applied to the currently indexed > > > + address range. > > > + > > > +bit (4) : #define ETM_MODE_BB > > > +description : Set to enable branch broadcast if supported in hardware [IDR0]. > > > + > > > +bit (5) : #define ETMv4_MODE_CYCACC > > > +description : Set to enable cycle accurate trace if supported [IDR0]. > > > + > > > +bit (6) : ETMv4_MODE_CTXID > > > +description : Set to enable context ID tracing if supported in hardware [IDR2]. > > > + > > > +bit (7) : ETM_MODE_VMID > > > +description : Set to enable virtual machine ID tracing if supported [IDR2]. > > > + > > > +bit (11) : ETMv4_MODE_TIMESTAMP > > > +description : Set to enable timestamp generation if supported [IDR0]. > > > + > > > +bit (12) : ETM_MODE_RETURNSTACK > > > +description : Set to enable trace return stack use if supported [IDR0]. > > > + > > > +bit (13-14) : ETM_MODE_QELEM(val) > > > +description : ‘val’ determines level of Q element support enabled if > > > + implemented by the ETM [IDR0] > > > + > > > +bit (19) : ETM_MODE_ATB_TRIGGER > > > +description : Set to enable the ATBTRIGGER bit in the event control register > > > + [EVENTCTLR1] if supported [IDR5]. > > > + > > > +bit (20) : ETM_MODE_LPOVERRIDE > > > +description : Set to enable the LPOVERRIDE bit in the event control register > > > + [EVENTCTLR1], if supported [IDR5]. > > > + > > > +bit (21) : ETM_MODE_ISTALL_EN > > > +description : Set to enable the ISTALL bit in the stall control register > > > + [STALLCTLR] > > > + > > > +bit (23) : ETM_MODE_INSTPRIO > > > +description : Set to enable the INSTPRIORITY bit in the stall control register > > > + [STALLCTLR] , if supported [IDR0]. > > > + > > > +bit (24) : ETM_MODE_NOOVERFLOW > > > +description : Set to enable the NOOVERFLOW bit in the stall control register > > > + [STALLCTLR], if supported [IDR3]. > > > + > > > +bit (25) : ETM_MODE_TRACE_RESET > > > +description : Set to enable the TRCRESET bit in the viewinst control register > > > + [VICTLR] , if supported [IDR3]. > > > + > > > +bit (26) : ETM_MODE_TRACE_ERR > > > +description : Set to enable the TRCCTRL bit in the viewinst control register > > > + [VICTLR]. > > > + > > > +bit (27) : ETM_MODE_VIEWINST_STARTSTOP > > > +description : Set the initial state value of the ViewInst start / stop logic > > > + in the viewinst control register [VICTLR] > > > + > > > +bit (30) : ETM_MODE_EXCL_KERN > > > +description : Set default trace setup to exclude kernel mode trace (see note a) > > > + > > > +bit (31) : ETM_MODE_EXCL_USER > > > +description : Set default trace setup to exclude user space trace (see note a) > > > + > > > +Note a) On startup the ETM is programmed to trace the complete address space > > > +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to > > > +set EL exclude bits for NS state in either user space (EL0) or kernel space > > > +(EL1) in the address range comparator. (the default setting excludes all > > > +secure EL, and NS EL2) > > > + > > > +Once the reset parameter has been used, and/or custom programming has been > > > +implemented - using these bits will result in the EL bits for address > > > +comparator 0 being set in the same way. > > > + > > > +Note b) Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with > > > +data trace. As A profile data trace is architecturally prohibited in ETMv4, > > > +these have been omitted here. Possible uses could be where a kernel has > > > +support for control of R or M profile infrastructure as part of a heterogeneous > > > +system. > > > + > > > +Bits 17, 28-29 are unused. > > > + > > > diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight/coresight.txt > > > similarity index 100% > > > rename from Documentation/trace/coresight.txt > > > rename to Documentation/trace/coresight/coresight.txt > > > diff --git a/MAINTAINERS b/MAINTAINERS > > > index 783569e3c4b4..777b77fde29b 100644 > > > --- a/MAINTAINERS > > > +++ b/MAINTAINERS > > > @@ -1582,8 +1582,7 @@ R: Suzuki K Poulose <suzuki.poulose@arm.com> > > > L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) > > > S: Maintained > > > F: drivers/hwtracing/coresight/* > > > -F: Documentation/trace/coresight.txt > > > -F: Documentation/trace/coresight-cpu-debug.txt > > > +F: Documentation/trace/coresight/* > > > F: Documentation/devicetree/bindings/arm/coresight.txt > > > F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt > > > F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* > > > -- > > > 2.17.1 > > > > > > > -- > Mike Leach > Principal Engineer, ARM Ltd. > Manchester Design Centre. UK
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 36258bc1b473..112c50ae9986 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -1,4 +1,4 @@ -What: /sys/bus/coresight/devices/<memory_map>.etm/enable_source +What: /sys/bus/coresight/devices/etm<N>/enable_source Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> @@ -8,82 +8,82 @@ Description: (RW) Enable/disable tracing on this specific trace entiry. of coresight components linking the source to the sink is configured and managed automatically by the coresight framework. -What: /sys/bus/coresight/devices/<memory_map>.etm/cpu +What: /sys/bus/coresight/devices/etm<N>/cpu Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) The CPU this tracing entity is associated with. -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_pe_cmp +What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of PE comparator inputs that are available for tracing. -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_addr_cmp +What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of address comparator pairs that are available for tracing. -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_cntr +What: /sys/bus/coresight/devices/etm<N>/nr_cntr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of counters that are available for tracing. -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ext_inp +What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates how many external inputs are implemented. -What: /sys/bus/coresight/devices/<memory_map>.etm/numcidc +What: /sys/bus/coresight/devices/etm<N>/numcidc Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of Context ID comparators that are available for tracing. -What: /sys/bus/coresight/devices/<memory_map>.etm/numvmidc +What: /sys/bus/coresight/devices/etm<N>/numvmidc Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of VMID comparators that are available for tracing. -What: /sys/bus/coresight/devices/<memory_map>.etm/nrseqstate +What: /sys/bus/coresight/devices/etm<N>/nrseqstate Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of sequencer states that are implemented. -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_resource +What: /sys/bus/coresight/devices/etm<N>/nr_resource Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of resource selection pairs that are available for tracing. -What: /sys/bus/coresight/devices/<memory_map>.etm/nr_ss_cmp +What: /sys/bus/coresight/devices/etm<N>/nr_ss_cmp Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Indicates the number of single-shot comparator controls that are available for tracing. -What: /sys/bus/coresight/devices/<memory_map>.etm/reset +What: /sys/bus/coresight/devices/etm<N>/reset Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (W) Cancels all configuration on a trace unit and set it back to its boot configuration. -What: /sys/bus/coresight/devices/<memory_map>.etm/mode +What: /sys/bus/coresight/devices/etm<N>/mode Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> @@ -91,302 +91,349 @@ Description: (RW) Controls various modes supported by this ETM, for example P0 instruction tracing, branch broadcast, cycle counting and context ID tracing. -What: /sys/bus/coresight/devices/<memory_map>.etm/pe +What: /sys/bus/coresight/devices/etm<N>/pe Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls which PE to trace. -What: /sys/bus/coresight/devices/<memory_map>.etm/event +What: /sys/bus/coresight/devices/etm<N>/event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3. -What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren +What: /sys/bus/coresight/devices/etm<N>/event_instren Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the behavior of the events in bank 0 to 3. -What: /sys/bus/coresight/devices/<memory_map>.etm/event_ts +What: /sys/bus/coresight/devices/etm<N>/event_ts Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the insertion of global timestamps in the trace streams. -What: /sys/bus/coresight/devices/<memory_map>.etm/syncfreq +What: /sys/bus/coresight/devices/etm<N>/syncfreq Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls how often trace synchronization requests occur. -What: /sys/bus/coresight/devices/<memory_map>.etm/cyc_threshold +What: /sys/bus/coresight/devices/etm<N>/cyc_threshold Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Sets the threshold value for cycle counting. -What: /sys/bus/coresight/devices/<memory_map>.etm/bb_ctrl +What: /sys/bus/coresight/devices/etm<N>/bb_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls which regions in the memory map are enabled to use branch broadcasting. -What: /sys/bus/coresight/devices/<memory_map>.etm/event_vinst +What: /sys/bus/coresight/devices/etm<N>/event_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls instruction trace filtering. -What: /sys/bus/coresight/devices/<memory_map>.etm/s_exlevel_vinst +What: /sys/bus/coresight/devices/etm<N>/s_exlevel_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. -What: /sys/bus/coresight/devices/<memory_map>.etm/ns_exlevel_vinst +What: /sys/bus/coresight/devices/etm<N>/ns_exlevel_vinst Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) In non-secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level. -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_idx +What: /sys/bus/coresight/devices/etm<N>/addr_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which address comparator or pair (of comparators) to work with. -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_instdatatype +What: /sys/bus/coresight/devices/etm<N>/addr_instdatatype Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls what type of comparison the trace unit performs. -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_single +What: /sys/bus/coresight/devices/etm<N>/addr_single Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Used to setup single address comparator values. -What: /sys/bus/coresight/devices/<memory_map>.etm/addr_range +What: /sys/bus/coresight/devices/etm<N>/addr_range Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Used to setup address range comparator values. -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_idx +What: /sys/bus/coresight/devices/etm<N>/seq_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which sequensor. -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_state +What: /sys/bus/coresight/devices/etm<N>/seq_state Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Use this to set, or read, the sequencer state. -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_event +What: /sys/bus/coresight/devices/etm<N>/seq_event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Moves the sequencer state to a specific state. -What: /sys/bus/coresight/devices/<memory_map>.etm/seq_reset_event +What: /sys/bus/coresight/devices/etm<N>/seq_reset_event Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Moves the sequencer to state 0 when a programmed event occurs. -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_idx +What: /sys/bus/coresight/devices/etm<N>/cntr_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which counter unit to work with. -What: /sys/bus/coresight/devices/<memory_map>.etm/cntrldvr +What: /sys/bus/coresight/devices/etm<N>/cntrldvr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) This sets or returns the reload count value of the specific counter. -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_val +What: /sys/bus/coresight/devices/etm<N>/cntr_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) This sets or returns the current count value of the specific counter. -What: /sys/bus/coresight/devices/<memory_map>.etm/cntr_ctrl +What: /sys/bus/coresight/devices/etm<N>/cntr_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the operation of the selected counter. -What: /sys/bus/coresight/devices/<memory_map>.etm/res_idx +What: /sys/bus/coresight/devices/etm<N>/res_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which resource selection unit to work with. -What: /sys/bus/coresight/devices/<memory_map>.etm/res_ctrl +What: /sys/bus/coresight/devices/etm<N>/res_ctrl Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Controls the selection of the resources in the trace unit. -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_idx +What: /sys/bus/coresight/devices/etm<N>/ctxid_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which context ID comparator to work with. -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_pid +What: /sys/bus/coresight/devices/etm<N>/ctxid_pid Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Get/Set the context ID comparator value to trigger on. -What: /sys/bus/coresight/devices/<memory_map>.etm/ctxid_masks +What: /sys/bus/coresight/devices/etm<N>/ctxid_masks Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Mask for all 8 context ID comparator value registers (if implemented). -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_idx +What: /sys/bus/coresight/devices/etm<N>/vmid_idx Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Select which virtual machine ID comparator to work with. -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_val +What: /sys/bus/coresight/devices/etm<N>/vmid_val Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Get/Set the virtual machine ID comparator value to trigger on. -What: /sys/bus/coresight/devices/<memory_map>.etm/vmid_masks +What: /sys/bus/coresight/devices/etm<N>/vmid_masks Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (RW) Mask for all 8 virtual machine ID comparator value registers (if implemented). -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcoslsr +What: /sys/bus/coresight/devices/etm<N>/addr_exlevel_s_ns +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Set the Exception Level matching bits for secure and + non-secure exception levels. + +What: /sys/bus/coresight/devices/etm<N>/vinst_pe_cmp_start_stop +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Access the start stop control register for PE input + comparators. + +What: /sys/bus/coresight/devices/etm<N>/addr_cmp_view +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (R) Print the current settings for the selected address + comparator. + +What: /sys/bus/coresight/devices/etm<N>/sshot_idx +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Select the single shot control register to access. + +What: /sys/bus/coresight/devices/etm<N>/sshot_ctrl +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Access the selected single shot control register. + +What: /sys/bus/coresight/devices/etm<N>/sshot_status +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (R) Print the current value of the selected single shot + status register. + +What: /sys/bus/coresight/devices/etm<N>/sshot_pe_ctrl +Date: August 2019 +KernelVersion: 5.4 +Contact: Mathieu Poirier <mathieu.poirier@linaro.org> +Description: (RW) Access the selected single show PE comparator control + register. + +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcoslsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the OS Lock Status Register (0x304). The value it taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdcr +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdcr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Power Down Control Register (0x310). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpdsr +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpdsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Power Down Status Register (0x314). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trclsr +What: /sys/bus/coresight/devices/etm<N>/mgmt/trclsr Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the SW Lock Status Register (0xFB4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcauthstatus +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcauthstatus Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Authentication Status Register (0xFB8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevid +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevid Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Device ID Register (0xFC8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcdevtype +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Device Type Register (0xFCC). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr0 +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr0 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Peripheral ID0 Register (0xFE0). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr1 +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr1 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Peripheral ID1 Register (0xFE4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr2 +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr2 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Peripheral ID2 Register (0xFE8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcpidr3 +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcpidr3 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the Peripheral ID3 Register (0xFEC). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trcconfig +What: /sys/bus/coresight/devices/etm<N>/mgmt/trcconfig Date: February 2016 KernelVersion: 4.07 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the trace configuration register (0x010) as currently set by SW. -What: /sys/bus/coresight/devices/<memory_map>.etm/mgmt/trctraceid +What: /sys/bus/coresight/devices/etm<N>/mgmt/trctraceid Date: February 2016 KernelVersion: 4.07 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Print the content of the trace ID register (0x040). -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr0 +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr0 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the tracing capabilities of the trace unit (0x1E0). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr1 +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr1 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the tracing capabilities of the trace unit (0x1E4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr2 +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr2 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> @@ -394,7 +441,7 @@ Description: (R) Returns the maximum size of the data value, data address, VMID, context ID and instuction address in the trace unit (0x1E8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr3 +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr3 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> @@ -403,42 +450,42 @@ Description: (R) Returns the value associated with various resources architecture specification for more details (0x1E8). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr4 +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr4 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns how many resources the trace unit supports (0x1F0). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr5 +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr5 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns how many resources the trace unit supports (0x1F4). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr8 +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr8 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the maximum speculation depth of the instruction trace stream. (0x180). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr9 +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr9 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the number of P0 right-hand keys that the trace unit can use (0x184). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr10 +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr10 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> Description: (R) Returns the number of P1 right-hand keys that the trace unit can use (0x188). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr11 +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr11 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> @@ -446,7 +493,7 @@ Description: (R) Returns the number of special P1 right-hand keys that the trace unit can use (0x18C). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr12 +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr12 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> @@ -454,7 +501,7 @@ Description: (R) Returns the number of conditional P1 right-hand keys that the trace unit can use (0x190). The value is taken directly from the HW. -What: /sys/bus/coresight/devices/<memory_map>.etm/trcidr/trcidr13 +What: /sys/bus/coresight/devices/etm<N>/trcidr/trcidr13 Date: April 2015 KernelVersion: 4.01 Contact: Mathieu Poirier <mathieu.poirier@linaro.org> diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight/coresight-cpu-debug.txt similarity index 100% rename from Documentation/trace/coresight-cpu-debug.txt rename to Documentation/trace/coresight/coresight-cpu-debug.txt diff --git a/Documentation/trace/coresight/coresight-etm4x-reference.txt b/Documentation/trace/coresight/coresight-etm4x-reference.txt new file mode 100644 index 000000000000..72e81bbbef43 --- /dev/null +++ b/Documentation/trace/coresight/coresight-etm4x-reference.txt @@ -0,0 +1,459 @@ +ETMv4 sysfs linux driver programming reference - v2. +==================================================== + +Supplement to existing ETMv4 driver documentation. + +Sysfs files and directories +--------------------------- + +Root: /sys/bus/coresight/devices/etm<N> + + +The following paragraphs explain the association between sysfs files and the +ETMv4 registers that they effect. Note the register names are given without +the ‘TRC’ prefix. + +File : mode (rw) +Trace Registers : {CONFIGR + others} +Notes : Bit select trace features. See ‘mode’ section below. Bits + in this will cause equivalent programming of trace config and + other registers to enable the features requested. +Syntax & eg : 'echo bitfield > mode' + bitfield up to 32 bits setting trace features. +Example : $> echo 0x > mode + +File : reset (wo) +Trace Registers : All +Notes : Reset all programming to trace nothing / no logic programmed. +Syntax : 'echo 1 > reset' + +File : enable_source (wo) +Trace Registers : PRGCTLR, All hardware regs. +Notes : >0: Programs up the hardware with the current values held in + the driver and enables trace. + 0: disable trace hardware. +Syntax : 'echo 1 > enable_source' + +File : cpu (ro) +Trace Registers : None. +Notes : CPU ID that this ETM is attached to. +Example :$> cat cpu + $> 0 + +File : addr_idx (rw) +Trace Registers : None. +Notes : Virtual register to index address comparator and range + features. Set index for first of the pair in a range. +Syntax : 'echo idx > addr_idx' + Where idx < nr_addr_cmp x 2 + +File : addr_range (rw) +Trace Registers : ACVR[idx, idx+1], VIIECTLR +Notes : Pair of addresses for a range selected by addr_idx. Include + / exclude according to the optional parameter, or if omitted + uses the current ‘mode’ setting. Select comparator range in + control register. Error if index is odd value. +Depends : mode, addr_idx +Syntax : 'echo addr1 addr2 [exclude] > addr_range' + Where addr1 and addr2 define the range and addr1 < addr2. + Optional exclude value - 0 for include, 1 for exclude. +Example : $> echo 0x0000 0x2000 0 > addr_range + +File : addr_single (rw) +Trace Registers : ACVR[idx] +Notes : Set a single address comparator according to addr_idx. This + is used if the address comparator is used as part of event + generation logic etc. +Depends : addr_idx +Syntax : 'echo addr1 > addr_single' + +File : addr_start (rw) +Trace Registers : ACVR[idx], VISSCTLR +Notes : Set a trace start address comparator according to addr_idx. + Select comparator in control register. +Depends : addr_idx +Syntax : 'echo addr1 > addr_start' + +File : addr_stop (rw) +Trace Registers : ACVR[idx], VISSCTLR +Notes : Set a trace stop address comparator according to addr_idx. + Select comparator in control register. +Depends : addr_idx +Syntax : 'echo addr1 > addr_stop' + +File : addr_context (rw) +Trace Registers : ACATR[idx,{6:4}] +Notes : Link context ID comparator to address comparator addr_idx +Depends : addr_idx. +Syntax : 'echo ctxt_idx > addr_context' + Where ctxt_idx is the index of the linked context id / vmid + comparator. + +File : addr_ctxtype (rw) +Trace Registers : ACATR[idx,{3:2}] +Notes : Input value string. Set type for linked context ID comparator +Depends : addr_idx +Syntax : 'echo type > addr_ctxtype' + Type one of {all, vmid, ctxid, none} +Example : $> echo ctxid > addr_ctxtype + +File : addr_exlevel_s_ns (rw) +Trace Registers : ACATR[idx,{14:8}] +Notes : Set the ELx secure and non-secure matching bits for the + selected address comparator +Depends : addr_idx +Syntax : 'echo val > addr_exlevel_s_ns' + val is a 7 bit value for exception levels to exclude. Input + value shifted to correct bits in register. +Example : $> echo 0x4F > addr_exlevel_s_ns + +File : addr_instdatatype (rw) +Trace Registers : ACATR[idx,{1:0}] +Notes : Set the comparator address type for matching. Driver only + supports setting instruction address type. +Depends : addr_idx + +File : addr_cmp_view (ro) +Trace Registers : ACVR[idx, idx+1], ACATR[idx], VIIECTLR +Notes : Read the currently selected address comparator. If part of + address range then display both addresses. +Depends : addr_idx +Syntax : 'cat addr_cmp_view' +Example : $> cat addr_cmp_view + addr_cmp[0] range 0x0 0xffffffffffffffff include ctrl(0x4b00) + +File : nr_addr_cmp (ro) +Trace Registers : From IDR4 +Notes : Number of address comparator pairs + +File : sshot_idx (rw) +Trace Registers : None +Notes : Select single shot register set. + +File : sshot_ctrl (rw) +Trace Registers : SSCCR[idx] +Notes : Access a single shot comparator control register. +Depends : sshot_idx +Syntax : 'echo val > sshot_ctrl' + Writes val into the selected control register. + +File : sshot_status (ro) +Trace Registers : SSCSR[idx] +Notes : Read a single shot comparator status register +Depends : sshot_idx +Syntax : 'cat sshot_status' + Read status. +Example : $> cat sshot_status + 0x1 + +File : sshot_pe_ctrl (rw) +Trace Registers : SSPCICR[idx] +Notes : Access a single shot PE comparator input control register. +Depends : sshot_idx +Syntax : echo val > sshot_pe_ctrl + Writes val into the selected control register. + +File : ns_exlevel_vinst (rw) +Trace Registers : VICTLR{23:20} +Notes : Program non-secure exception level filters. Set / clear NS + exception filter bits. Setting ‘1’ excludes trace from the + exception level. +Syntax : 'echo bitfield > ns_exlevel_viinst' + Where bitfield contains bits to set clear for EL0 to EL2 +Example : %> echo 0x4 > ns_exlevel_viinst + ; Exclude EL2 NS trace. + +File : vinst_pe_cmp_start_stop (rw) +Trace Registers : VIPCSSCTLR +Notes : Access PE start stop comparator input control registers + +File : bb_ctrl (rw) +Trace Registers : BBCTLR +Notes : Define ranges that Branch Broadcast will operate in. + Default (0x0) is all addresses. +Depends : BB enabled. + +File : cyc_threshold (rw) +Trace Registers : CCCTLR +Notes : Set the threshold for which cycle counts will be emitted. + Error if attempt to set below minimum defined in IDR3, masked + to width of valid bits. +Depends : CC enabled. + +File : syncfreq (rw) +Trace Registers : SYNCPR +Notes : Set trace synchronisation period. Power of 2 value, 0 (off) + or 8-20. Driver defaults to 12 (every 4096 bytes). + +File : cntr_idx (rw) +Trace Registers : none +Notes : Select the counter to access +Syntax : 'echo idx > cntr_idx' + Where idx < nr_cntr + +File : cntr_ctrl (rw) +Trace Registers : CNTCTLR[idx] +Notes : Set counter control value +Depends : cntr_idx +Syntax : 'echo val > cntr_ctrl' + Where val is per ETMv4 spec. + +File : cntrldvr (rw) +Trace Registers : CNTRLDVR[idx] +Notes : Set counter reload value +Depends : cntr_idx +Syntax : 'echo val > cntrldvr' + Where val is per ETMv4 spec. + +File : nr_cntr (ro) +Trace Registers : From IDR5 +Notes : Number of counters implemented. + +File : ctxid_idx (rw) +Trace Registers : None +Notes : Select the context ID comparator to access +Syntax : 'echo idx > ctxid_idx' + Where idx < numcidc + +File : ctxid_pid (rw) +Trace Registers : CIDCVR[idx] +Notes : Set the context ID comparator value +Depends : ctxid_idx + +File : ctxid_masks (rw) +Trace Registers : CIDCCTLR0, CIDCCTLR1, CIDCVR<0-7> +Notes : Pair of values to set the byte masks for 1-8 context ID + comparators. Automatically clears masked bytes to 0 in CID + value registers. +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > ctxid_masks' + 32 bit values made up of mask bytes, where mN represents a + byte mask value for Ctxt ID comparator N. + Second value not required on systems that have fewer than 4 + context ID comparators + +File : numcidc (ro) +Trace Registers : From IDR4 +Notes : Number of Context ID comparators + +File : vmid_idx (rw) +Trace Registers : None +Notes : Select the VM ID comparator to access. +Syntax : 'echo idx > vmid_idx' + Where idx < numvmidc + +File : vmid_val (rw) +Trace Registers : VMIDCVR[idx] +Notes : Set the VM ID comparator value +Depends : vmid_idx + +File : vmid_masks (rw) +Trace Registers : VMIDCCTLR0, VMIDCCTLR1, VMIDCVR<0-7> +Notes : Pair of values to set the byte masks for 1-8 VM ID + comparators. Automatically clears masked bytes to 0 in VMID + value registers. +Syntax : 'echo m3m2m1m0 [m7m6m5m4] > vmid_masks' + Where mN represents a byte mask value for VMID comparator N. + Second value not required on systems that have fewer than + 4 VMID comparators. + +File : numvmidc (ro) +Trace Registers : From IDR4 +Notes : Number of VMID comparators + +File : res_idx (rw) +Trace Registers : None. +Notes : Select the resource selector control to access. Must be 2 or + higher as selectors 0 and 1 are hardwired. +Syntax : 'echo idx > res_idx' + Where 2 <= idx < nr_resource x 2 + +File : res_ctrl (rw) +Trace Registers : RSCTLR[idx] +Notes : Set resource selector control value. Value per ETMv4 spec. +Depends : res_idx +Syntax : 'echo val > res_cntr' + Where val is per ETMv4 spec. + +File : nr_resource (ro) +Trace Registers : From IDR4 +Notes : Number of resource selector pairs + +File : event (rw) +Trace Registers : EVENTCTRL0R +Notes : Set up to 4 implemented event fields. +Syntax : 'echo ev3ev2ev1ev0 > event' + Where evN is an 8 bit event field. Up to 4 event fields make up + the 32bit input value. Number of valid fields implementation + dependent defined in IDR0. + +File : event_instren (rw) +Trace Registers : EVENTCTRL1R +Notes : Choose events which insert event packets into trace stream. +Depends : EVENTCTRL0R +Syntax : 'echo bitfield > event_instren' + Where bitfield is up to 4 bits according to number of event + fields. + +File : event_ts (rw) +Trace Registers : TSCTLR +Notes : Set the event that will generate timestamp requests. +Depends : TS activated +Syntax : 'echo evfield > event_ts' + Where evfield is an 8 bit event selector. + +File : seq_idx (rw) +Trace Registers : None +Notes : Sequencer event register select - 0 to 2 + + +File : seq_state (rw) +Trace Registers : SEQSTR +Notes : Sequencer current state - 0 to 3. + +File : seq_event (rw) +Trace Registers : SEQEVR[idx] +Notes : State transition event registers +Depends : seq_idx +Syntax : 'echo evBevF > seq_event' + Where evBevF is a 16 bit value made up of two event selectors, + evB - back, evF - forwards. + +File : seq_reset_event (rw) +Trace Registers : SEQRSTEVR +Notes : Sequencer reset event +Syntax : 'echo evfield > seq_reset_event' + Where evfield is an 8 bit event selector. + +File : nrseqstate (ro) +Trace Registers : From IDR5 +Notes : Number of sequencer states (0 or 4) + +File : nr_pe_cmp (ro) +Trace Registers : From IDR4 +Notes : Number of PE comparator inputs + +File : nr_ext_inp (ro) +Trace Registers : From IDR5 +Notes : Number of external inputs + +File : nr_ss_cmp (ro) +Trace Registers : From IDR4 +Notes : Number of Single Shot control registers + +Note: When programming any address comparator the driver will tag the +comparator with a type used - i.e. RANGE, SINGLE, START, STOP. Once this tag +is set, then only the values can be changed using the same sysfs file / type +used to program it. + +Thus:- +% echo 0 > addr_idx ; select address comparator 0 +% echo 0x1000 0x5000 0 > addr_range ; set address range on comparators 0 and 1. +% echo 0x2000 > addr_start ; this will error as comparator 0 is a + ; range comparator +% echo 2 > addr_idx ; select address comparator 2 +% echo 0x2000 > addr_start ; this is OK as comparator 2 is unused, +% echo 0x3000 > addr_stop ; this will error as comparator 2 a start + ; address comparator +% echo 2 > addr_idx ; select address comparator 3 +% echo 0x3000 > addr_stop ; this is OK + +To remove programming on all the comparators (and all the other hardware) use +the reset parameter: + +% echo 1 > reset + +The ‘mode’ sysfs parameter. +--------------------------- + +This is a bitfield selection parameter that sets the overall trace mode for the +ETM. The table below describes the bits, using the defines from the driver +source file, along with a description of the feature these represent. Many +features are optional and therefore dependent on implementation in the +hardware. + +Bit assignements shown below:- + +bit (0) : #define ETM_MODE_EXCLUDE +description : This is the default value for the include / exclude function when + setting address ranges. Set 1 for exclude range. When the mode + parameter is set this value is applied to the currently indexed + address range. + +bit (4) : #define ETM_MODE_BB +description : Set to enable branch broadcast if supported in hardware [IDR0]. + +bit (5) : #define ETMv4_MODE_CYCACC +description : Set to enable cycle accurate trace if supported [IDR0]. + +bit (6) : ETMv4_MODE_CTXID +description : Set to enable context ID tracing if supported in hardware [IDR2]. + +bit (7) : ETM_MODE_VMID +description : Set to enable virtual machine ID tracing if supported [IDR2]. + +bit (11) : ETMv4_MODE_TIMESTAMP +description : Set to enable timestamp generation if supported [IDR0]. + +bit (12) : ETM_MODE_RETURNSTACK +description : Set to enable trace return stack use if supported [IDR0]. + +bit (13-14) : ETM_MODE_QELEM(val) +description : ‘val’ determines level of Q element support enabled if + implemented by the ETM [IDR0] + +bit (19) : ETM_MODE_ATB_TRIGGER +description : Set to enable the ATBTRIGGER bit in the event control register + [EVENTCTLR1] if supported [IDR5]. + +bit (20) : ETM_MODE_LPOVERRIDE +description : Set to enable the LPOVERRIDE bit in the event control register + [EVENTCTLR1], if supported [IDR5]. + +bit (21) : ETM_MODE_ISTALL_EN +description : Set to enable the ISTALL bit in the stall control register + [STALLCTLR] + +bit (23) : ETM_MODE_INSTPRIO +description : Set to enable the INSTPRIORITY bit in the stall control register + [STALLCTLR] , if supported [IDR0]. + +bit (24) : ETM_MODE_NOOVERFLOW +description : Set to enable the NOOVERFLOW bit in the stall control register + [STALLCTLR], if supported [IDR3]. + +bit (25) : ETM_MODE_TRACE_RESET +description : Set to enable the TRCRESET bit in the viewinst control register + [VICTLR] , if supported [IDR3]. + +bit (26) : ETM_MODE_TRACE_ERR +description : Set to enable the TRCCTRL bit in the viewinst control register + [VICTLR]. + +bit (27) : ETM_MODE_VIEWINST_STARTSTOP +description : Set the initial state value of the ViewInst start / stop logic + in the viewinst control register [VICTLR] + +bit (30) : ETM_MODE_EXCL_KERN +description : Set default trace setup to exclude kernel mode trace (see note a) + +bit (31) : ETM_MODE_EXCL_USER +description : Set default trace setup to exclude user space trace (see note a) + +Note a) On startup the ETM is programmed to trace the complete address space +using address range comparator 0. ‘mode’ bits 30 / 31 modify this setting to +set EL exclude bits for NS state in either user space (EL0) or kernel space +(EL1) in the address range comparator. (the default setting excludes all +secure EL, and NS EL2) + +Once the reset parameter has been used, and/or custom programming has been +implemented - using these bits will result in the EL bits for address +comparator 0 being set in the same way. + +Note b) Bits 2-3, 8-10, 15-16, 18, 22, control features that only work with +data trace. As A profile data trace is architecturally prohibited in ETMv4, +these have been omitted here. Possible uses could be where a kernel has +support for control of R or M profile infrastructure as part of a heterogeneous +system. + +Bits 17, 28-29 are unused. + diff --git a/Documentation/trace/coresight.txt b/Documentation/trace/coresight/coresight.txt similarity index 100% rename from Documentation/trace/coresight.txt rename to Documentation/trace/coresight/coresight.txt diff --git a/MAINTAINERS b/MAINTAINERS index 783569e3c4b4..777b77fde29b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1582,8 +1582,7 @@ R: Suzuki K Poulose <suzuki.poulose@arm.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/hwtracing/coresight/* -F: Documentation/trace/coresight.txt -F: Documentation/trace/coresight-cpu-debug.txt +F: Documentation/trace/coresight/* F: Documentation/devicetree/bindings/arm/coresight.txt F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
Update existing docs for new sysfs API features. Add new ETMv4 reference document for sysfs programming. Move coresight documentation to common directory. Signed-off-by: Mike Leach <mike.leach@linaro.org> --- .../testing/sysfs-bus-coresight-devices-etm4x | 183 ++++--- .../{ => coresight}/coresight-cpu-debug.txt | 0 .../coresight/coresight-etm4x-reference.txt | 459 ++++++++++++++++++ .../trace/{ => coresight}/coresight.txt | 0 MAINTAINERS | 3 +- 5 files changed, 575 insertions(+), 70 deletions(-) rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%) create mode 100644 Documentation/trace/coresight/coresight-etm4x-reference.txt rename Documentation/trace/{ => coresight}/coresight.txt (100%)