| Message ID | 20190823145015.15974-1-will@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [BOOTWRAPPER] Enable TME for lower exception levels | expand |
On Fri, Aug 23, 2019 at 03:50:15PM +0100, Will Deacon wrote: > By default, TME is not available to exception levels below EL3, so > enable it in SCR_EL3 if we detect that it is implemented. > > Signed-off-by: Will Deacon <will@kernel.org> Applied, thanks! Mark. > --- > arch/aarch64/boot.S | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > index 74705cded338..c2fe92c90297 100644 > --- a/arch/aarch64/boot.S > +++ b/arch/aarch64/boot.S > @@ -48,6 +48,13 @@ _start: > orr x0, x0, #(1 << 16) // AP key enable > orr x0, x0, #(1 << 17) // AP insn enable > 1: > + /* Enable TME if present */ > + mrs x1, id_aa64isar0_el1 > + ubfx x1, x1, #24, #4 > + cbz x1, 1f > + > + orr x0, x0, #(1 << 34) // TME enable > +1: > #ifndef KERNEL_32 > orr x0, x0, #(1 << 10) // 64-bit EL2 > #endif > -- > 2.11.0 >
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 74705cded338..c2fe92c90297 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -48,6 +48,13 @@ _start: orr x0, x0, #(1 << 16) // AP key enable orr x0, x0, #(1 << 17) // AP insn enable 1: + /* Enable TME if present */ + mrs x1, id_aa64isar0_el1 + ubfx x1, x1, #24, #4 + cbz x1, 1f + + orr x0, x0, #(1 << 34) // TME enable +1: #ifndef KERNEL_32 orr x0, x0, #(1 << 10) // 64-bit EL2 #endif
By default, TME is not available to exception levels below EL3, so enable it in SCR_EL3 if we detect that it is implemented. Signed-off-by: Will Deacon <will@kernel.org> --- arch/aarch64/boot.S | 7 +++++++ 1 file changed, 7 insertions(+)